Switching Transition Control to Improve Efficiency of a DC/DC Power Electronic System

Abstract

Increasing the switching frequency of the power semiconductor devices (PSDs) reduces the size and cost of the passive elements, thereby positively affecting the power density of a high-frequency (HF) power electronic system (PES). To achieve a higher switching frequency of a PES, yet low switching losses, the speed of switching transitions of PSDs need to be increased. However, such fast transitions adversely affect PES performance in terms of electromagnetic interference (EMI) and device stress. Hence, a switching transition control (STC) scheme is developed to create optimality between switching PSDs with higher transitions yet maintaining safe levels of parasitic oscillations, that result from reducing the transition time of these devices. The switching transition control (STC) framework helps the HF PES achieve a target efficiency improvement by controlling the high di/dt and dv/dt regions of a PSD on the fly. Results are shown to validate that this improvement of efficiency is not feasible with a passive gate drive. An HF Ćuk PES using a Cree SiC MOSFET half-bridge module is fabricated for the testing purpose of the STC framework. The STC network is based on a simple switched resistor network, synthesized using high-speed GaN-FETs and built across two generations, Gen-1, and Gen-2. Practical operational issues of the STC network with fast switching GaN-FET in the Gen-1 board are analyzed and are overcome with design modification in Gen-2. The work has ramifications in meeting a system-level goal of an HF WBG PES, like a target efficiency increment, while not deteriorating the EMI performance and PSD stress levels that result due to parasitic oscillations in such PES.INDEX TERMS Switching transition control (STC), PSD, EMI, half-bridge, GaN FET, target efficiency.

High-Power Design Challenges for Differential-Mode EV Universal Battery Supercharger

“…Fast transition of switch voltage and current reduces the switching loss and thermal requirements, however it in turn causes current and voltage oscillation due to parasitic capacitance and inductance in the circuit. One way to address this challenge is in the gate driver by slowing down the device passively or actively during the fast transitions [8], [20], [21]. Alternatively, the printed circuit board or the bus bar parasites can be optimized and mitigated to enhance the high speed behavior [7], [9], [10], [14].…”