Switched Capacitor Filters

Taylor, R. C.

doi:10.1007/978-1-4757-2353-3_11

Cited by 3 publications

(3 citation statements)

References 6 publications

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“…Dummy capacitors surround the array. Interconnect lines extend on both sides of unit capacitors to reduce errors due to H4 G4 F1 G1 H1 3 4 5 3 4 F6 D4 C1 D1 F3 5 2 5 2 5 E4 B4 A1 B1 E1 4 2 1 3 3 E2 B2 A2 B3 E3 3 4 1 2 4 F4 D2 C2 D3 F5 5 2 5 2 5 H2 G2 F2 G3 H3 4 3 5 [11]. Routing depends on cell assignment.…”

Section: (B)mentioning

confidence: 98%

“…Special layout techniques exist to realize a noninteger value of unit-capacitors that preserves the same area-to-perimeter ratio. For example, i-1 capacitors are realized using unit square cells, while the last non-unit capacitor is a rectangular-shaped capacitor with a hole to control the capacitor perimeter [11], this technique is adopted since it requires only two adjacent cells.…”

Section: Cell Assignmentmentioning

confidence: 99%

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Automatic generation of common-centroid capacitor arrays with arbitrary capacitor ratio

Sayed

Dessouky

Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition

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The key performance of many analog circuits is directly related to accurate capacitor ratios. It is well known that capacitor ratio precision is greatly enhanced by paralleling identical size unit capacitors in a commoncentroid geometry. In this paper, a general algorithm for fitting arbitrary capacitor ratios in a common-centroid unit-capacitor array is presented. The algorithm gives special care to both non-integer and identical ratios in order to minimize mismatch. A method for capacitance mismatch estimation based upon an oxide gradient model is also introduced. It enables the comparison of different unit-capacitor array assignments. Layout issues are discussed with emphasis on a generic routing model. Both the algorithm and the mismatch estimation method are implemented in an automatic capacitor array generation tool.

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Section: (B)mentioning

confidence: 98%

Section: Cell Assignmentmentioning

confidence: 99%

Automatic generation of common-centroid capacitor arrays with arbitrary capacitor ratio

Sayed

Dessouky

Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition

View full text Add to dashboard Cite

show abstract

“…It is well known that using parallel unit capacitors has a great effect in reducing ratio mismatch [1]. In addition, commoncentroid geometries are considered particularly important to reduce mismatch and achieve high accuracy as they help reducing the effects of gradients and random errors in fabrication [2].…”

Section: Introductionmentioning

confidence: 99%

Evaluation of Capacitor Ratios in Automated Accurate Common-Centroid Capacitor Arrays

Khalil¹,

Dessouky²,

Bourguet³

et al.

Sixth International Symposium on Quality of Electronic Design (ISQED'05)

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In this paper, design and measurement results of a test chip that intends to evaluate differences between layout techniques for rectangular unit-capacitor arrays are introduced. Precision capacitor ratios are compared using a switched-capacitor biquad and a pseudo-floating gate configuration. The test chip is used to evaluate the effectiveness of an automatic common-centroid capacitor array generation tool with arbitrary capacitor ratios. Results indicate significant improvements in ratio accuracy, which have a direct impact on a wide range of applications such as filters for wireless communications, hard drives, and high precision baseband processing.

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Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors

Lin

Chiu

et al. 2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Switched Capacitor Filters

Cited by 3 publications

References 6 publications

Automatic generation of common-centroid capacitor arrays with arbitrary capacitor ratio

Automatic generation of common-centroid capacitor arrays with arbitrary capacitor ratio

Evaluation of Capacitor Ratios in Automated Accurate Common-Centroid Capacitor Arrays

Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors

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