Over the past couple of decades, the digital design technology scales to date remarkably satisfying the Moore's Law. The circuits became denser with the scaling of transistor and interconnect, and operating frequencies increased several orders of magnitudes during this period. This poses challenges to digital circuit design in a variety of areas including clock distribution, power management, process migration, fault-tolerance, etc. A lot of research effort goes to tackle these issues under the synchronous design methodology which currently dominates the digital design world. However, the magnitude of the challenges poised has also revitalized the asynchronous design methodology explored in this work, as it inherently address some of key issues. The main philosophy of the asynchronous design practices is to compose a digital circuit as a collection of autonomous parts communicating with each other locally, as opposed to synchronous design which controls the circuit with a centralized clock signal. Without a global clock or clock domains the designs eliminate the ever increasing problems of high power and area consumption, skew minimization, etc. associated with the clocks. Each component operates only when required in an inherently power efficient manner generating a low electromagnetic(EM) noise. The control and data flow is inherently elastic providing immunity to transistor-to-transistor variability in the manufacturing process, thus providing better technology migration characteristics. These are only a few of the main advantages of asynchronous design. The spectrum of design styles under asynchronous paradigm varies from bundled data communication model which can employ synchronous-like data processing elements with careful delay matching for completion detection, to delay-insensitive model which can accommodate arbitrary delays in the design. The focus of the is work is on the former style-the bundled data model-which is more close to synchronous design practices. Synchronous circuits, specially pipelined circuits can be transformed to these form asynchronous designs with relative ease. In a time when digital design primarily done in synchronous manner, the work presented here will be significant in harnessing the strengths of asynchronous practices by migrating from synchronous to asynchronous with low effort. This PhD dissertation presents is a new pipeline controller based on Early Acknowledgement protocol for bundled data asynchronous circuits. The Early Acknowledgement protocol is a hybrid of 2-phase and 4-phase handshake protocols, two widely used protocols This work would not be possible without the immense support extended my advisor Prof. Tomohiro Yoneda. He was always available for help and guided me in the right direction. The informal, friendly and productive environment created by him was a key to this success. I would also like to thank my wife, Indu who stood by me all along, always supporting me throughout this period. I am ever thankful for her to for taking a greater share of responsibilit...
