Survey of oxide degradation in inverter circuits using 2.0 nm MOS devices

Degradation of Rise Time in NAND Gates Using 2.0 nm Gate Dielectrics

“…Since only the pMOSFET experiences wearout, a change in tf is not expected nor is observed. This follows the results of undamaged nMOSFET response in inverters [4]. Additionally, results observed for wearout support the work of Carter et al, in which an increased time delay is simulated in the NAND gate time-domain response (Fig.…”

“…Similar results obtained through the study of inverter circuits demonstrate pMOSFET wearout is responsible for increased tr [4]. Ultimately, the increase in rise time may affect the critical timing path of digital logic circuits such as clocked registers, which depend on precise timing to function properly.…”

“…Inverter circuit degradation attributed to dielectric wearout or breakdown mechanisms have received recent attention [1][2][3][4][5][6][7][8], yet reports on physical (i.e., not simulated) oxide degradation effects on other logic gates, such as the NAND gate, are minimal. Furthermore, much of the work on inverter reliability has focused on the change of dc voltage transfer characteristics following circuit stressing without investigating the time domain [1,2,7,8].…”

“…This has yet to be investigated in other logic gates including NAND gates. Hence, the switch matrix technique is used to study time domain NAND gate reliability in this paper. It has been proposed by Ogas et al that traditional gate oxide breakdown (GOB) events, such as soft breakdown (SBD) or hard breakdown (HBD), need not occur for circuit performance to deteriorate [4]. Similarly, Carter et al suggest logic circuits are affected dynamically by gate oxide degradation through their simulation of NAND gates and full adder circuit models [10].…”

Impact of single pMOSFET dielectric degradation on NAND circuit performance

“…The effects of dielectric breakdown mechanisms on inverter circuit performance have received recent attention [1][2][3][4][5][6][7][8], yet experimental results (i.e., not simulated) on these effects on other logic gates, such as the NAND gate, are negligible. Furthermore, the focus of reliability studies on the inverter logic circuit has involved the detrimental aspects of a circuit level stress on the DC voltage transfer characteristics (VTC) exclusive of circuit response in the time-domain [1,2,7,8].…”