Survey of Dynamically Reconfigurable Network-on-Chip

Gu, Haiyun

doi:10.1109/icfcsa.2011.52

Cited by 7 publications

(7 citation statements)

References 8 publications

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“…CoNoChi generates a routing table whenever topology changes and tables are then distributed via the network. In DRAFT, a hierarchal level dependent mask is used by each router to determine if the received flit is to be moved upward [7].…”

Section: Related Workmentioning

confidence: 99%

Adaptive routing framework for network on chip architectures

Mustafa

Öztürk

Niar

2016

Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools

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In this paper we suggest and demonstrate the idea of applying multiple routing algorithms during the execution of a real application mapped on a Network-on-Chip (NoC). Traffic pattern of a real application may change during its execution. As performance of an algorithm depends on the traffic pattern, using the same routing algorithm for the entire span of execution may be inefficient. We study the feasibility of this idea for applications such as SPARSE and MPEG-4 decoder, by applying different routing algorithms. By applying more than one routing algorithms, throughput improves up to 17.37% and 6.74% in the case of SPARSE and MPEG-4 decoder applications, respectively, as compared to the application of single routing algorithm.

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Section: Related Workmentioning

confidence: 99%

Adaptive routing framework for network on chip architectures

Mustafa

Öztürk

Niar

2016

Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools

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“…(1) best solution = ∞ (2) population = generate random population(PZ) (3) ∀ population, fitness = 1/comm cost (4) while generation ≤ NG do (5) while ≤ PZ do (6) cr sel1, cr sel2 = roulette(population, fitness) (7) if (crossover) then (8) Offspring( ) = Crossover(cr sel1, cr sel2) (9) Offspring( + 1) = Crossover(cr sel2, cr sel1) (10) else (11) Offspring( ) = cr sel1 (12) Offspring( + 1) = cr sel2 (13) end if (14) if (mutation) then (15) Offspring( ) = mutate(cr sel1) (16) Offspring( + 1) = mutate(cr sel2) (17) end if (18) for , + 1 do (19) if offspring( ).maps then (20) fitness = 1/comm cost (21) else ( previous population is killed. If a better solution is found, it is saved at the end of iteration.…”

Section: General Structurementioning

confidence: 99%

“…Although methodologies and tools have been proposed [6][7][8], to deal with the increased design complexity of this class of circuits, solutions to the associated problems are still very ad hoc.…”

Section: Introductionmentioning

confidence: 99%

Using Genetic Algorithms for Hardware Core Placement and Mapping in NoC-Based Reconfigurable Systems

Filho

Strum

Chau

2015

International Journal of Reconfigurable Computing

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Mapping of cores has been an important activity in NoC-based system design aimed to find the best topological location onto the NoC, such that the metrics of interest can be greatly optimized. In the last years, partial reconfigurable systems (PRSs) have included Networks-on-Chips (NoCs) as their communication structure, adding complexity to the problem of mapping. Several works have proposed specific and robust NoC architectures for PRSs, forming indirect and irregular networks, in which cases the mapping and placement problems must be treated altogether. The placement deals with the physical positioning of those cores inside the reconfigurable device. Up to now, to the best of our knowledge, the mapping-placement problem for those kinds of architectures has not been addressed yet. In this work, the problem formalization for the design-time hardware core placement and mapping in PRS-NoCs is proposed and methodologies for solving it with genetic algorithms (GAs) are presented. Several GA crossovers and methodologies are compared for obtaining the best solution. Results have shown that best GA solution obtained, in average, communication costs with 4% of penalty when compared with global minimum cost, obtained in a semiexhaustive approach. In addition, the algorithm presents low execution times.

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“…Such a one-chip integrated circuit, referred to as System-on-Chip (SoC) is made up of a set of embedded cores that communicate with each other via a network of long dedicated connections implemented, for instance, as shared bus lines [23], [24], [28]. In parallel, the idea of data exchange between modules of the integrated circuit via a Network-on-Chip (NoC) has become pretty popular over the recent years [13], [33], [25], [10], [5], [20], [17], [8], [12]. But anyway, interconnections between nodes of such a network are usually implemented as an internal bus.…”

Section: Introductionmentioning

confidence: 99%

New Structure of Test Pattern Generator Stimulating Crosstalks in Bus-type Connections

Garbolino

2015

International Journal of Electronics and Telecommunications

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Abstract-The paper discloses the idea of a new structure for a Test Pattern Generator (TPG) for detection of crosstalk faults that may happen to bus-type interconnections between built-in blocks within a System-on-Chip structure. The new idea is an improvement of the TPG design proposed by the author in one of the previous studies. The TPG circuit is meant to generate test sequences that guarantee detection of all crosstalk faults with the capacitive nature that may occur between individual lines within an interconnecting bus. The study comprises a synthesizable and parameterized model developed for the presented TPG in the VLSI Hardware Description Language (VHDL) with further investigation of properties and features of the offered module. The significant advantages of the proposed TPG structure include less area occupied on a chip and higher operation frequency as compared to other solutions. In addition, the design demonstrates good scalability in terms of both the hardware overhead and the length of the generated test sequence. This study is dedicated to an innovative structure of a test pattern generator aimed at stimulation of crosstalk faults that may happen to bus-type connections. The fully scalable and synthesizable model of such a TPG unit has been developed in the VHDL language. The model was subjected to thorough investigations with regard to the length of the output test sequence and the associated hardware overhead. KeywordsThe TPG disclosed in this study is an improved option of the solution already described in [9]. The new design of the TPG benefits from reduction in length of the shift register and alteration of the test vector counter. These measures made it possible to achieve a TPG structure that highlights with less hardware overhead and much higher operation frequency than the solution presented in [9].

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Survey of Dynamically Reconfigurable Network-on-Chip

Cited by 7 publications

References 8 publications

Adaptive routing framework for network on chip architectures

Adaptive routing framework for network on chip architectures

Using Genetic Algorithms for Hardware Core Placement and Mapping in NoC-Based Reconfigurable Systems

New Structure of Test Pattern Generator Stimulating Crosstalks in Bus-type Connections

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