Surface Properties from Transconductance in Nanoscale Systems

Abstract

Because of the continued scaling of transistor dimensions and incorporation of nanostructured materials into modern electronic and optoelectronic devices, surfaces and interfaces have become a dominant factor dictating material properties and device performance. In this study, we investigate the temperature-dependent electronic transport properties of InAs nanowire field-effect transistors. A point where the nanowire conductance becomes independent of temperature is observed, known as the zero-temperature-coefficient. The distribution of surface states is determined by a spectral analysis of the conductance activation energy and used to develop a carrier transport model that explains the existence and gate voltage dependence of this point. We determine that the position of this point in gate voltage is directly related to the fixed oxide charge on the nanowire surface and demonstrate the utility of this method for studying surface passivations in nanoscale systems by characterizing (NH)S and H plasma surface treatments on InAs nanowires.

Sensing Responses Based on Transfer Characteristics of InAs Nanowire Field-Effect Transistors

“…For our NWFET in N 2 (i.e., without adsorbates), we find . Given that in this case, each e of charge corresponds directly to a single allowed electron state, this value is in good agreement with previous work on the surface state density of InAs surfaces [ 27 , 41 ]. The values of in various analytes are summarized in Table 1 along with other transport parameters.…”

“…Inter-digitated electrical contacts were then defined by electron beam lithography on a spin-coated PMMA resist layer. Ti (20 )/Au (90 ) metal was deposited onto the substrate following an evaporation and lift-off procedure described elsewhere [ 41 ]. The inter-digital spacing defines the channel length and was nominally 2 ; however, following metal deposition, the average length was measured as 1.8 .…”

“…As the curves tend to inflect through this region, this corresponds with the peak values of transconductance ( ) as determined by numerical differentiation. The following equations were employed [ 41 ]: where L is channel length, R is NW radius, is back-gate dielectric thickness and is the effective permittivity of the SiO 2 gate dielectric modified by the geometric arrangement [ 41 ]. Gate capacitances were calculated in (2) by considering a parallel configuration of each NW channel formed and applying a Gaussian distribution to the NW radii.…”

Rethinking the Characterization of Nanoscale Field‐Effect Transistors: A Universal Approach

“…When considering the gate voltage dependence of transport properties, the experimental V g sweep rate ( V ′) is often ignored in literature, which affects the determination of transport characteristics due to electrical hysteresis (i.e., G ( V g ) depends on the direction and value of V ′). This is observed in various semiconductor NWs, [ 24,40–45 ] thin films, [ 46–48 ] and carbon nanotubes, [ 49–54 ] and is often related to slow localized states. These states exchange charge with the conduction band at a delayed rate causing time dependent measurements of G ( V g ).…”

“…In the literature devoted to nanowire (NW) FET structures (see ref. [ 24,56,57 ] ), authors often replace C with the well‐known expression for the capacitance between a metallic cylinder and plate where a is the NW radius, d is the gate dielectric thickness, and ε eff is the effective dielectric constant of the surrounding medium (for SiO 2 films ε eff ≃ 2.12 [ 40 ] ). A wrapped gate NW FET uses the simple formula for a cylinderical capacitor: .…”