Surface Preparation Challenge on Nitrided Gate Oxides

Photoresist degradation can occur during wet etching processes due to chemicals diffusion through the polymer. The adhesion of the resist is not guaranteed anymore and damage on the resist / material interface appears. This phenomenon is usually monitored by optical methods. However, invisible resist degradation cannot be detected and the physical nature of the resist / material modification remains unknown. A high-frequency acoustic echography method has been developed to overcome these problems and has been performed to study the apparition of blisters in a deep UV photoresist exposed to a Standard Clean 1 solution. This technique allows the quantitative detection of resist degradation even if blisters cannot be seen in the resist. It has also been found that gas pockets appear during blisters formation.

Section: Resultsmentioning

confidence: 99%

“…Wet etching in photoresist presence is commonly used in MEMS or integrated circuits manufacturing: metal gates (1), or gate oxides patterning (2). For few sensitive operations, it is still more preferred towards plasma etching, and enables a better surface smoothness control.…”

Section: Introductionmentioning

confidence: 99%

Acoustic Characterization of Patterning Degradation during Wet Etching

Virgilio¹,

Garnier²,

Foucaud³

et al. 2015

“…[1] High temperature PNA contributes to improve the device performance. As CMOS technology scales, more investigation demonstrated that the PNA was expected as a post "oxidation" process to repair the interface defects by the substrate oxidization and minimize interfacial nitrogen [2][3] [4] . The physical model for improvement is new SiO 2 bonds growing at the Si interface during the annealing.…”

Section: Two Steps Pnamentioning

confidence: 99%

Two Steps Post Nitridation Anneal Study

Zhao¹,

Tang

Zhao³

2012

In sub-micrometer devices, nitrogen is incorporated into the gateoxide to reduce gate leakage current density and prevent boron penetration. This gate-stack technology includes base-oxide growth, decoupled plasma nitridation (DPN), and post nitridation anneal (PNA) which stabilizes the nitrogen into SiON chemical bonds. The effect of the PNA in reducing the gate leakage and improving the device reliability by raising the annealing temperature has been previously demonstrated. A two-steps PNA process has been developed which can achieve the requisite of device properties, such like leakage, threshold voltage and NBTI, gate oxide integrity (GOI), etc., while enabling EOT scaling. In this paper, the two-steps PNA process parameters impact on interface-traps density, and Idsat is presented.

“…This paper demonstrates the same or better electrical performance can be obtained on single wafer tools. State of the art 65 nm gate oxide grown on 300mm have been considered, integrated in a Double or Triple Gate Oxides flow [4].…”

Section: Motivationmentioning

confidence: 99%

Gate Oxide Cleans on Single Wafer Tool

Garnier¹,

Vessa²,

Larrea³

et al. 2007

Pre gate oxide and especially "Double Gate Oxide" cleans are the most critical surface preparation steps in the semiconductor industry. This paper describes the key parameters to perform this kind of operations on a fully integrated single wafer cleaning tool. This switch from conventional batch cleaning tool enables significant defect density reduction and therefore yield enhancement. Nonetheless the main challenge of the double gate oxide clean is the prevention and the control of photo lithography resist lift off during the wet etch. This clean is also composed of two other steps, less critical. Nonetheless special care has been considered in the surface preparation in order to avoid any electrical mobility degradation.