In the context of Industry 4.0, the demand for the mass production of highly customized products will lead to complex products and an increasing demand for production system flexibility. Simply implementing lean production-based human-centered production or high automation to improve system flexibility is insufficient. Currently, lean automation (Jidoka) that utilizes cyber-physical systems (CPS) is considered a cost-efficient and effective approach for improving system flexibility under shrinking global economic conditions. Therefore, a smart lean automation engine enabled by CPS technologies (SLAE–CPS), which is based on an analysis of Jidoka functions and the smart capacity of CPS technologies, is proposed in this study to provide an integrated and standardized approach to design and implement a CPS-based smart Jidoka system. A set of comprehensive architecture and standardized key technologies should be presented to achieve the above-mentioned goal. Therefore, a distributed architecture that joins service-oriented architecture, agent, function block (FB), cloud, and Internet of things is proposed to support the flexible configuration, deployment, and performance of SLAE–CPS. Then, several standardized key techniques are proposed under this architecture. The first one is for converting heterogeneous physical data into uniform services for subsequent abnormality analysis and detection. The second one is a set of Jidoka scene rules, which is abstracted based on the analysis of the operator, machine, material, quality, and other factors in different time dimensions. These Jidoka rules can support executive FBs in performing different Jidoka functions. Finally, supported by the integrated and standardized approach of our proposed engine, a case study is conducted to verify the current research results. The proposed SLAE–CPS can serve as an important reference value for combining the benefits of innovative technology and proper methodology.
Aiming at the phenomenon of bottleneck shifting in job shop, this article presents the findings on the coupling relationship among the bottleneck shifting factors. We first defined the chain probability to show the relation that the change of one bottleneck shifting factor causes the changes of other factors in job shop. Then, we used three variables (time-capability, time-load, and quality-assurance) and the transaction probability to describe the changes of the factors. Considering the interaction among the bottleneck shifting factors, we established the independent contributions and comprehensive contributions, showing how the changes of various shifting factors may impact the bottleneck shifting phenomenon interactively. Finally, an instance of analysis of the coupling relation of several bottleneck shifting factors in some job shop is given to test the validity and rationality of the method established in this research.
As the planar CMOS transistor devices scaling down, a lot of original process have to be optimized, developed or changed to meet the evolutional requirement, and the new process elements were continuously implemented into the manufacture. The STIliner is one of the processes from the STI module, which comes after the trench etch and before the trench gap-fill, to provide an excellent interface and good adhesion between the silicon and the oxide. While the device scaling down, some device issues, such as, the incident of dislocations which impacted on the device leakage current, the dopant segregation which result in the threshold voltage variation and impact the inverse narrow width effect (INWE) and the gate oxide integrity (GOI), etc, are associated with the STI module and can be improved by the STI-liner process. The STI liner process is evolved from the furnace oxidation, the dry RTO, the nitrided oxide liner to the ISSG.
Aggressive scaling of planar bulk CMOS device has resulted in the need for ultra-shallow junctions (USJ) formation. This represents some special concern are not only integration solution, but also the individual process precise control to meet the evolutional requirements. In the USJ particular, as junction thickness (depth) decreases, the series resistance of the junction increases. Therefore, the dopants concentration must to be increased to improve the resistance. Dilemma, the diffusion is an important issue in shallow junction technology. The spike anneal process was widely adopted at advanced CMOS fabrication to meet the device requirements. In this paper, how to precisely control the processes of spike anneal is discussed. The two major interacted process factors, peak-temperature and residence-time must be separately tunable, not only to meet the requirements of device parameter, but also to achieve an operational precise controlling for process setup, optimization and maintenance.
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