2010
DOI: 10.1049/el.2010.2781
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Surface passivation of AlN/GaN MOS-HEMTs using ultra-thin Al2O3 formed by thermal oxidation of evaporated aluminium

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Cited by 21 publications
(10 citation statements)
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“…It is clear that a 20-sec Al etch has a significant impact on the device performance with the drain current at zero gate voltage (I DSS ) more than double that of a device in which the etching time was 10 secs. Compared to similar results for the AlN/GaN HEMT (unprotected and unpassivated device in Figure 6(b)) on the same epilayer structure, these results show that protecting and passivating the AlN/GaN layers during processing yield AlN/GaN MOS-HEMT with far superior and excellent transistor characteristics [6].…”
Section: Gate Wrap-around Mos-hemt Optimisationsupporting
confidence: 67%
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“…It is clear that a 20-sec Al etch has a significant impact on the device performance with the drain current at zero gate voltage (I DSS ) more than double that of a device in which the etching time was 10 secs. Compared to similar results for the AlN/GaN HEMT (unprotected and unpassivated device in Figure 6(b)) on the same epilayer structure, these results show that protecting and passivating the AlN/GaN layers during processing yield AlN/GaN MOS-HEMT with far superior and excellent transistor characteristics [6].…”
Section: Gate Wrap-around Mos-hemt Optimisationsupporting
confidence: 67%
“…A new process for the fabrication AlN/GaN-based devices was therefore developed. It involved employing thermally grown Al 2 O 3 for protection of the very sensitive AlN epilayer from exposure to liquid chemicals during processing [6] as earlier described for TLM experiments (Figure 2). This Al 2 O 3 , which is formed by thermal oxidation of evaporated Al, acts as a surface passivate and as a gate dielectric for the transistors.…”
Section: Gate Wrap-around Mos-hemt Optimisationmentioning
confidence: 99%
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“…Perhaps for this reason, as well as application-driven thermal requirements, published HEMT substrate thicknesses have been reported as thin as 25 µm for CVD diamond, 100 µm for SiC, to even 1 mm for silicon [4,18,21]. Published material also has a wide range of GaN thicknesses for application-driven electrical, and perhaps thermal requirements, ranging from 0.47 µm to 3.8 µm and even up to 9 µm [21][22][23].…”
Section: Figure 2: (A) Gan Hemt Device (Not To Scale) (B) Simplified mentioning
confidence: 99%