Supporting Utilities for Heterogeneous Embedded Image Processing Platforms (STHEM): An Overview

Sadek, A.; Muddukrishna, Ananya; Kalms, Lester; Djupdal, A.; Podlubne, Ariel; Paolillo, Antonio; Goehringer, Diana; Jahre, Magnus

doi:10.1007/978-3-319-78890-6_59

Cited by 15 publications

(14 citation statements)

References 11 publications

(10 reference statements)

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“…The Tulipp EU (STHEM) (Available online: https://github.com/tulipp-eu/sthem (accessed on 1 October 2019)) project (Available online: http://tulipp.eu/ (accessed on 30 September 2019)) provides an electronic hardware measurement platform with a power measurement utility (PMU) [22]. It has a built-in field programmable gate array (FPGA) power analysis tool.…”

Section: System Modelmentioning

confidence: 99%

Energy and Performance Trade-Off Optimization in Heterogeneous Computing via Reinforcement Learning

Machado

Zahid

et al. 2020

Electronics

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This paper suggests an optimisation approach in heterogeneous computing systems to balance energy power consumption and efficiency. The work proposes a power measurement utility for a reinforcement learning (PMU-RL) algorithm to dynamically adjust the resource utilisation of heterogeneous platforms in order to minimise power consumption. A reinforcement learning (RL) technique is applied to analyse and optimise the resource utilisation of field programmable gate array (FPGA) control state capabilities, which is built for a simulation environment with a Xilinx ZYNQ multi-processor systems-on-chip (MPSoC) board. In this study, the balance operation mode for improving power consumption and performance is established to dynamically change the programmable logic (PL) end work state. It is based on an RL algorithm that can quickly discover the optimization effect of PL on different workloads to improve energy efficiency. The results demonstrate a substantial reduction of 18% in energy consumption without affecting the application’s performance. Thus, the proposed PMU-RL technique has the potential to be considered for other heterogeneous computing platforms.

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Section: System Modelmentioning

confidence: 99%

Energy and Performance Trade-Off Optimization in Heterogeneous Computing via Reinforcement Learning

Machado

Zahid

et al. 2020

Electronics

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“…The Supporting uTilities for Heterogeneous EMbedded (STHEM) image processing platform [10] automates iterative, and otherwise tedious and time consuming FPGA HLS steps such as performance evaluation, design space exploration and vendor-specific HLS tool configuration. The goal is to allow the system designer to concentrate on just the main application development steps.…”

Section: ) Loop Pipeliningmentioning

confidence: 99%

Towards Automatic High-Level Code Deployment on Reconfigurable Platforms: A Survey of High-Level Synthesis Tools and Toolchains

et al. 2020

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Heterogeneous computing systems with tightly coupled processors and reconfigurable logic blocks provide great scope to improve software performance by executing each section of code on the processor or custom hardware accelerator that best matches its requirements and the system optimisation goals. This paper is motivated by the idea of a software tool that can automatically accomplish the task of deploying code, originally written for a conventional computer, to the processors and reconfigurable logic blocks in a heterogeneous system. We undertake an extensive survey of high-level synthesis tools to determine how close we are to this vision, and to identify any capability gaps. The survey is structured according to a new framework that clearly expresses the relationships between the many tools surveyed. We find that none of the existing tools can deploy general high-level code without manual intervention. Logic synthesis from arbitrary high-level code remains an open problem with dynamic data structures, function pointers and recursion all presenting challenges. Other challenges include automating the tasks of code partitioning, optimisation and design space exploration.

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“…Cornil et al [4] assessed the research challenges to face with this kind of platforms. Ahmad et al [20] provided tools to optimise the design of real-time applications running on reconfigurable devices (with regards to different metrics such as performance and energy consumption). Pagani et al [17] proposed the integration of Dynamic Partial Reconfiguration (DPR, a technique to reconfigure an FPGA at run-time) as part of a provided service of operating systems Biondi et al [2,3] provided several timing analyses and run-time framework works that make use of DPR, enabling reconfigurable heterogeneous platforms as target candidates for real-time systems.…”

Section: Related Workmentioning

confidence: 99%

“…We generate approximately 1 000 feasible task sets with utilisations ∈ (p − 0.1, p], where we increase p from 0.6 to 1.0 in steps of 0.1. The deadlines are uniformly chosen in the range [1,20]. As a scheduler, we use Global-RM and remove any nonschedulable taskset from our experiments.…”

Section: Empirical Pessimism Of Reconfiguredmentioning

confidence: 99%

Acceptor

Goossens

Poczekajlo

Paolillo

et al. 2019

Proceedings of the 27th International Conference on Real-Time Networks and Systems

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In this work, we consider hard real-time applications scheduled upon heterogeneous multiprocessor platforms. The originality of this study is to consider multi-mode real-time applications (software aspects) and reconfigurable-heterogeneous hardware platforms (composed of CPUs, GPUs, FPGAs. . . ). Our approach is based on a multi-mode protocol, for mode-dependent tasks upon reconfigurable hardware. The goal is to handle predictable switches between different task sets and different hardware settings. The novelty here is the dynamic hardware and software reconfigurability. First, we propose a formal model of the applications and reconfigurable hardware platforms. We then propose and prove correct a mode change protocol. We propose in particular a validity test for the verification of the timing constraints of the application -including the time allowed to complete a mode change. We also perform a complete evaluation. We study the theoretical complexity of the protocol, use a simulation to evaluate the efficiency of our solution, and finally propose a competitive analysis of our protocol to prove that it is 2-competitive. CCS CONCEPTS• Computer systems organization → Real-time systems; Multicore architectures.

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Supporting Utilities for Heterogeneous Embedded Image Processing Platforms (STHEM): An Overview

Cited by 15 publications

References 11 publications

Energy and Performance Trade-Off Optimization in Heterogeneous Computing via Reinforcement Learning

Energy and Performance Trade-Off Optimization in Heterogeneous Computing via Reinforcement Learning

Towards Automatic High-Level Code Deployment on Reconfigurable Platforms: A Survey of High-Level Synthesis Tools and Toolchains

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