The detection of moving objects is a trivial task performed by vertebrate retinas, yet a complex computer vision task. Object-motion-sensitive ganglion cells (OMS-GC) are specialised cells in the retina that sense moving objects. OMS-GC take as input continuous signals and produce spike patterns as output, that are transmitted to the Visual Cortex via the optic nerve. The Hybrid Sensitive Motion Detector (HSMD) algorithm proposed in this work enhances the GSOC dynamic background subtraction (DBS) algorithm with a customised 3-layer spiking neural network (SNN) that outputs spiking responses akin to the OMS-GC. The algorithm was compared against existing background subtraction (BS) approaches, available on the OpenCV library, specifically on the 2012 change detection (CDnet2012) and the 2014 change detection (CDnet2014) benchmark datasets. The results show that the HSMD was ranked overall first among the competing approaches and has performed better than all the other algorithms on four of the categories across all the eight test metrics. Furthermore, the HSMD proposed in this paper is the first to use an SNN to enhance an existing state of the art DBS (GSOC) algorithm and the results demonstrate that the SNN provides near real-time performance in realistic applications.

This paper suggests an optimisation approach in heterogeneous computing systems to balance energy power consumption and efficiency. The work proposes a power measurement utility for a reinforcement learning (PMU-RL) algorithm to dynamically adjust the resource utilisation of heterogeneous platforms in order to minimise power consumption. A reinforcement learning (RL) technique is applied to analyse and optimise the resource utilisation of field programmable gate array (FPGA) control state capabilities, which is built for a simulation environment with a Xilinx ZYNQ multi-processor systems-on-chip (MPSoC) board. In this study, the balance operation mode for improving power consumption and performance is established to dynamically change the programmable logic (PL) end work state. It is based on an RL algorithm that can quickly discover the optimization effect of PL on different workloads to improve energy efficiency. The results demonstrate a substantial reduction of 18% in energy consumption without affecting the application’s performance. Thus, the proposed PMU-RL technique has the potential to be considered for other heterogeneous computing platforms.

For a considerable time, it has been the goal of computational neuroscientists to understand biological nervous systems. However, the vast complexity of such systems has made it very difficult to fully understand even basic functions such as movement. Because of its small neuron count, the C. elegans nematode offers the opportunity to study a fully described connectome and attempt to link neural network activity to behaviour. In this paper a simulation of the neural network in C. elegans that responds to chemical stimulus is presented and a consequent realistic head movement demonstrated. An evolutionary algorithm (EA) has been utilised to search for estimates of the values of the synaptic conductances and also to determine whether each synapse is excitatory or inhibitory in nature. The chemotaxis neural network was designed and implemented, using the parameterization obtained with the EA, on the Si elegans platform a state-of-the-art hardware emulation platform specially designed to emulate the C. elegans nematode.

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The world ageing population is increasing, giving rise to research targeted towards improving the quality of life and promoting the independent living of older adults. Detecting abnormalities in the daily activities of the older adults is relevant since abnormalities can be an early sign of health decline, prompting for the need for intervention. Current approaches to abnormality detection involve modelling the usual behavioural routine of the individual as a baseline and comparing subsequent behaviour to the baseline to detect abnormalities. This approach is prone to errors and not flexible since it does not take into account changes in human behavioural routine. Training is usually performed on pre-existing data making the abnormality detection model non-adaptive to new incoming data. An intermediary can be incorporated to enable model predictions to be communicated to humans for verification of the detected anomalies. This paper proposes a gesture recognition approach for facilitating interaction between humans and a robot intermediary. A model capable of recognising hand gestures corresponding to affirmations and denials is implemented. Preliminary evaluation shows that the proposed gesture recognition approach has the potential of being utilised in an assistive robot intermediary.

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For many decades neuroscience researchers have been interested in harnessing the computational power of the mammalian nervous system. However, the vast complexity of such a nervous system has made it very difficult to fully understand basic functions such as movement, touch and learning. More recently the nervous system of the C. elegans nematode has been widely studied and there now exists a vast wealth of biological knowledge about its nervous structure, function and connectivity. The Si elegans project aims to develop a Hardware Neural Network (HNN) to accurately replicate the C. elegans nervous system behavior to enable neuroscientists to better understand these basic functions. Replication of the C. elegans biological system requires powerful computing technologies, based on parallel processing, for real-time computation. The Si elegans project will use FPGAs due to their advanced programmable features that allow reconfigurability, high performance parallel processing and relatively low price per programmable logic element. Furthermore, the project will deliver an open-access framework that will be available via a Web Portal to neuroscientists, biologists, clinicians and engineers. In this paper an overview of the complete hardware system required to fully realize Si elegans is presented along with an early small scale implementation of the hardware system.