Supporting cache coherence in heterogeneous multiprocessor systems

Suh, Taeweon; Blough, Douglas M.; Lee, H.-H.S.

doi:10.1109/date.2004.1269047

Cited by 18 publications

(10 citation statements)

References 9 publications

(6 reference statements)

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“…Efficient sharing of data in a heterogeneous MpSoC which contains different types of integrated computational elements is a challenging task. Especially when private caches of CPU cores and dedicated memory of accelerators are used to store local copies of data, it is crucial to ensure that every processing element has a consistent view of the shared memory space [28], [18].…”

Section: Introductionmentioning

confidence: 99%

Energy and performance exploration of accelerator coherency port using Xilinx ZYNQ

Sadri

Weis

Wehn

et al. 2013

Proceedings of the 10th FPGAworld Conference

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Cooperation of CPU and hardware accelerator to accomplish computational intensive tasks, provides significant advantages in run-time speed and energy. Efficient management of data sharing among multiple computational kernels can rapidly turn into a complicated problem. The Accelerator coherency port (ACP) emerges as a possible solution by enabling hardware accelerators to issue coherent accesses to the memory space. In this paper, we quantify the advantages of using ACP over the traditional method of sharing data on the DRAM. We select the Xilinx ZYNQ as target and develop an infrastructure to stress the ACP and high-performance (HP) AXI interfaces of the ZYNQ device. Hardware accelerators on both of HP and ACP AXI interfaces reach full duplex data processing bandwidth of over 1.6 GBytes/s running at 125 MHz on a XC7Z020-1C device. The effect of background DRAM and cache traffic on the performance of accelerators is analyzed. For a sample image filtering task, the cooperative operation of CPU and ACP accelerator (CPU-ACP ) gains a speed-up of 1.2X over CPU and HP acceleration (CPU-HP ). In terms of energy efficiency, an improvement of 2.5 nJ (> 20%) is shown for each byte of processed data. This is the first work which represents detailed practical comparisons on the speed and energy efficiency of various processor-accelerator memory sharing techniques in a configurable heterogeneous platform.

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Section: Introductionmentioning

confidence: 99%

Energy and performance exploration of accelerator coherency port using Xilinx ZYNQ

Sadri

Weis

Wehn

et al. 2013

Proceedings of the 10th FPGAworld Conference

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“…A distributed, clustered LLC is deployed in 192 MB, organized into 6 banks; each bank is 8-way associative. Cache coherence is maintained by a directory-based MOESI protocol which supports heterogeneous transactions [50]. The onchip part connects to main memory through four 64-bit 533MHz DDR2 MC and 13Gb/s memory buses.…”

Section: Methodsmentioning

confidence: 99%

An Analytical Framework for Estimating Scale-Out and Scale-Up Power Efficiency of Heterogeneous Manycores

Yan

Han

et al. 2016

IEEE Trans. Comput.

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Heterogeneous manycore architectures have shown to be highly promising to boost power efficiency through two independent ways: 1) enabling massive thread-level parallelism, called "scale-out" approach, and 2) enabling thread migration between heterogeneous cores, called "scale-up" approach. How to accurately model the profitability of power efficiency of the two ways, particularly in an analytical and computational-effective manner, is essential to reap the power efficiency of such architectures. We propose a comprehensive analytical model to predict the power efficiency from the two independent ways. Given power efficiency is measured by performance per watt, this model is composed of a performance and a power model. The performance model is built by two orthogonal functions α and β. Function α describes the scale-out speedup from multithreading; function β presents the scale-up speedup from core heterogeneity. Thus, the performance model can clearly capture the overall speedup of any multithreading and thread-to-core mapping strategies. The power model predicts the power of corresponding scale-out and scale-up configurations. It simultaneously captures the power variations caused by thread synchronization and thread migration between heterogeneous cores. We build both performance and power model in an analytical way and keep the computational complexity in mind. This merit leads to a suit of comprehensive and low-complexity models for runtime management. These models are validated on large-scale heterogeneous manycore architecture with full-system simulations. For performance prediction, the average error is below 12%, lower than that of the state-of-the-art methods. For power prediction, the average error is 7.74%. On top of the models, we introduce two heuristic scheduling algorithms, performance-oriented MAX-P and power efficiency-oriented MAX-E, to demonstrate the usage of these models. The results show that MAX-P outperforms the state-of-the-art methods by 18% in performance averagely; MAX-E outperforms the baseline by 70% in power efficiency on average.

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“…In a bus-based MPSoC system [2], the cache controller is responsible for snooping the read/write operations carried out by the system bus or local core and updating the status of cached data. Several protocols such as MSI, MESI, Dragon and MOESI [3] are widely used in such systems.…”

Section: Introductionmentioning

confidence: 99%

End-to-End Delay Bounds Analysis of Different On-chip Cache Coherence Policies: A Network Calculus-Based Approch

Lai

Wang

2012

2012 Sixth Asia Modelling Symposium

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To analyze and compare end-to-end delay bounds of different cache coherence policies will provide beneficial guidelines for NoC design. However, it is not an easy task, because 1)packet flows generated by cache coherence events do not conform to the Poisson process, traditional queue theorem can't be applied to the performance analyzing for the NoCs that support cache coherence; 2) broadcast or multicast operations, which will duplicate the cache coherence packets, makes the analysis much more complicated. To address these challenges, in this paper, we use the stochastic network calculus to analyze the end-to-end delay bounds of different cache coherence policies. Specifically, we utilize Markovmodulated On-Off (MMOO) flow to model the arrival process of cache coherence events, and then deduce the general end-toend delay bounds for different cache coherence policies. Furthermore, to deal with packet duplication issues in broadcast or multicast operations, we develop an analytical model based on scaling functions to study their impacts on end-to-end delay bounds.

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Supporting cache coherence in heterogeneous multiprocessor systems

Abstract: In embedded system-on-a-chip (SoC)

Cited by 18 publications

References 9 publications

Energy and performance exploration of accelerator coherency port using Xilinx ZYNQ

Energy and performance exploration of accelerator coherency port using Xilinx ZYNQ

An Analytical Framework for Estimating Scale-Out and Scale-Up Power Efficiency of Heterogeneous Manycores

End-to-End Delay Bounds Analysis of Different On-chip Cache Coherence Policies: A Network Calculus-Based Approch

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