Supporting Analog Synthesis by Abstracting Circuit Behavior Using a Modeling Methodology

Jancke, Roland; Schwarz, Peter

doi:10.1109/iscas.2006.1692874

Cited by 2 publications

(3 citation statements)

References 7 publications

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“…Behavioral models and their construction using hardware description languages (HDLs) such as SystemC-AMS, VHDL-AMS, and Verilog-AMS for efficient AMS system design space exploration have become popular. The VHDL-AMS op-amp models presented in [35] and [36] take into account nonidealities such as parasitics. In [35], concepts of exploring analog design spaces with parasitic-included behavioral models were discussed.…”

Section: Related Prior Researchmentioning

confidence: 99%

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iVAMS 1.0: Polynomial-Metamodel-Integrated Intelligent Verilog-AMS for Fast, Accurate Mixed-Signal Design Optimization

Mohanty,

Kougianos

2019

Preprint

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Electronic circuit behavioral models built with hardware description/modeling languages such as Verilog-AMS for system-level simulations are typically functional models. They do not capture the physical design (layout) information of the target design. Thus, their applications are limited to early design feasibility studies and/or pre-layout functional verification. Numerous iterations of post-layout design adjustments are usually required to ensure that design specifications are met with the presence of layout parasitics. In this paper a paradigm shift of the current trend is presented that integrates layout-level information (with full parasitics) in Verilog-AMS through metamodels such that systemlevel simulation of a mixed-signal circuit/system is realistic and as accurate as true parasitic netlist simulation. The simulations performed with these parasitic-aware models can be used to estimate system performance without layout iterations. We call this new form of Verilog-AMS as iVAMS (i.e. Intelligent Verilog-AMS). We call this iVAMS 1.0 as it is simple polynomial-metamodel integrated Intelligent Verilog-AMS. As a specific case study, a voltage-controlled oscillator (VCO) Verilog-AMS behavioral model and design flow are proposed to assist fast PLL design space exploration. The PLL simulation employing quadratic metamodels achieves approximately 10× speedup compared to that employing the layout extracted, parasitic netlist. The simulations using this behavioral model attain high accuracy. The observed error for the simulated lock time and average power dissipation are 0.7 % and 3 %, respectively. This behavioral metamodel approach bridges the gap between layout-accurate but fast simulation and design space exploration. The proposed method also allows much shorter design verification and optimization to meet stringent time-to-market requirements. In the PLL optimization case study, 46 % PLL power reduction was achieved using a differential evolution algorithm and the proposed layout-accurate behavioral model. Compared to the optimization using the layout netlist, the runtime using the behavioral model is reduced by 88.9 %. To the best of the authors' knowledge this is the first approach that brings layout-level accuracy to system-level design exploration and is applied towards mixed-signal design exploration.

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Section: Related Prior Researchmentioning

confidence: 99%

“…The VHDL-AMS op-amp models presented in [35] and [36] take into account nonidealities such as parasitics. In [35], concepts of exploring analog design spaces with parasitic-included behavioral models were discussed. The model in [36] is valid with various loads and accounts for output nonlinear behavior.…”

Section: Related Prior Researchmentioning

confidence: 99%

iVAMS 1.0: Polynomial-Metamodel-Integrated Intelligent Verilog-AMS for Fast, Accurate Mixed-Signal Design Optimization

Mohanty,

Kougianos

2019

Preprint

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“…The use, however, of behavioral modeling at the system level presents a drawback that prevents widespread adoption of analogue synthesis system methodologies. Extraction or development of sub‐block models (Rutenbar et al , 2007; Jancke and Schwarz, 2006) may be difficult or too time consuming for many designers to adopt new design methodologies. Furthermore, simplistic models may fail to adequately capture sub‐block characteristics leading to poor results when final verification is completed with transistor‐level simulation.…”

Section: Introductionmentioning

confidence: 99%

Hierarchical synthesis system with hybrid DLO‐MOGA optimization

Scanlan

Halton

2011

COMPEL - The International Journal for Computation and Mathematics in Electrical and Electronic Engineering

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ABSTRACT:Purpose-The purpose of this paper is to present a hierarchical circuit synthesis system with a Hybrid DLO-MOGA (Deterministic Local Optimization -Multi-Objective Genetic Algorithm) optimization scheme for system level synthesis.Design/methodology/approach-The use of a local optimization with a deterministic algorithm based on linear equations which is computationally efficient and improves the feasibility of designs, allows reduction in the number of MOGA generations required to achieve convergence. Originality/value-The use of a Hybrid DLO-MOGA optimization approach is a new approach to improve hierarchical circuit synthesis time while preserving accuracy. Paper Type-Research Paper

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Supporting Analog Synthesis by Abstracting Circuit Behavior Using a Modeling Methodology

Cited by 2 publications

References 7 publications

iVAMS 1.0: Polynomial-Metamodel-Integrated Intelligent Verilog-AMS for Fast, Accurate Mixed-Signal Design Optimization

iVAMS 1.0: Polynomial-Metamodel-Integrated Intelligent Verilog-AMS for Fast, Accurate Mixed-Signal Design Optimization

Hierarchical synthesis system with hybrid DLO‐MOGA optimization

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