Supply and threshold-Voltage trends for scaled logic and SRAM MOSFETs

Morifuji, E.; Yoshida, Takeshi; Kanda, M.; Matsuda, Shôichi; Yamada, Shigeru; Matsuoka, F.

doi:10.1109/ted.2006.874752

Cited by 76 publications

(30 citation statements)

References 10 publications

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“…Smaller V TH leads to bigger leakage current [6,7]. The performance of SRAM would deteriorate as the bit-line leakage increases, and the read operation would even fail when the amount of leakage reaches a critical value [8,9,10,11]. To combat the adverse effect caused by the bit-line leakage, several methods and techniques have been proposed in [12,13,14,15,16].…”

Section: Introductionmentioning

confidence: 99%

Additive-calibration scheme for leakage compensation of low voltage SRAM

Peng

Lin

et al. 2016

IEICE Electron. Express

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As the bit-line leakage increases, the performance of SRAM will decline. Especially, the read operation will even fail when the amount of the leakage reaches a critical value. In this paper, we present a new technique, called Additive Calibration (AC), which can combat the bit-line leakage problem even in low voltage. Simulation results show that the maximum tolerant bit-line leakage current of our AC scheme is increased by 45.6% compared with the previous X-calibration scheme. Thus, this method can perform at higher frequency with much lower power consumption.

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Section: Introductionmentioning

confidence: 99%

Additive-calibration scheme for leakage compensation of low voltage SRAM

Peng

Lin

et al. 2016

IEICE Electron. Express

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“…The continuing miniature of the complementary metal oxide semiconductor (CMOS) technology has led to the exponential increase of the leakage power [1], [2]. Meanwhile, the dynamic power and delay of global interconnects increase with technology nodes scaling down, because the length of the global interconnects tends to increase with scaling [3], [4].…”

Section: Introductionmentioning

confidence: 99%

STT-MRAM based low power synchronous non-volatile logic with timing demultiplexing

Huang

Zhao

Lian

2014

Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale Architectures

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The high power and long global interconnection delay are two of the major limits for further scaling down of the process nodes in the very large scale integrated (VLSI) systems. Therefore, new technologies and computer architectures are under focused development to reduce the power consumption and interconnection delay. Magnetic tunnel junction (MTJ) nanopillar with the advantages of non-volatility, fast switching speed, and high density promises new designs and architectures to significantly alleviate the power and delay issues. This paper presents new logic-in-memory designs of the basic logic gates based on MTJs, including INV, (N)AND, (N)OR and XOR. The MTJ sharing and timing demultiplexing techniques are used in the proposed non-volatile logic gates to greatly reduce the write power. The simulation results show that the write power of the proposed non-volatile logic gates is as low as 285fJ/bit. The basic logic gates can finish the read operation in less than 160ps with 4.35fJ read energy. Moreover, the proposed non-volatile logic gates may be reconfigured after fabrication, which makes the designs more flexible and robust.

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“…Due to an aggressive down-scaling of CMOS transistors over recent years, the supply voltage V D and threshold voltage V T had to be reduced significantly to reduce the dynamic power, maintain the magnitude of the saturation current and assure a reliable operation for the devices [1][2][3][4]. 1 Therefore, from Eq.…”

Section: Introductionmentioning

confidence: 99%