SuperENC: MPEG-2 video encoder chip

A Software-Hardware Co-Implementation of MPEG-4 Advanced Video Coding (AVC) Decoder with Block Level Pipelining

“…The data communication between the processor and the dedicated hardware are processed via Direct Memory Access (DMA). In conclusion, the SW/HW joint optimization has been proven to enhance the performance of the video coding systems [9][10][11][12]. Thus, we maximize the throughput of the high complex AVC decoding system based on the SW/HW joint optimization.…”

“…Instead of the single chip approaches in [9] and [11], the authors in [10] have developed a scalable MPEG-2 Main Profile and Main Level (MP@ML) encoding scheme. The encoding throughput can be increased by deploying multiple chips for parallel processing.…”

“…Design methodology of SW/HW co-implementation has been widely adopted for realizing complicated multimedia systems [9][10][11][12]. The advantages of such design methodology can be shown from 3 different aspects including computational characteristics, design verification and system performance.…”

“…Thus, we use the SW/HW joint optimization to retain an optimized operation performance with moderate design efforts. Several video codec systems [9][10][11][12] have been developed using the SW/HW joint optimization approaches. The authors in [9] have developed a H.263 based videophone system with multiple micro-controllers, processors and dedicated hardware.…”

“…The optimization of the dedicated hardware design usually fits the target applications. As to the SW-HW coimplementation, we can achieve both fast development and high performance [9][10][11][12]. The SW/HW joint optimization is based on the characteristics of a multimedia system.…”