A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation

Abstract

This paper proposes a low-power systolic array architecture for a block-matching motion estimation processor IP for portable and high-resolution video applications. The architecture features a ringconnected processing element (PE) array to reduce both computation cycles and memory access cycles at the same time, allowing lower power characteristics. The feature of low memory access cycles allows concurrent operation of a half-pel processing unit with no extra cache. Furthermore, the architecture allows various summation schemes for absolute difference values. For that reason, it is applicable to various video coding modes such as the adaptive field/frame mode in MPEG2 and multiple macroblock mode in H.264. When the architecture is introduced to a design of a MPEG2 MP@HL motion estimation processor VLSI, the power consumption of the VLSI is reduced by 45-73% in comparison to cases with conventional architectures for motion estimation.

Reduced bit low power VLSI architectures for motion estimation

“…External memory accesses are also slower than the arithmetic unit on speed, and consume more power than the onchip memory [3]. Hence it may not be possible for an ordinary sequential processor to achieve this throughput while meeting the power constraints for mobile device applications [3,[11][12][13].…”

“…VLSI implementations of these fast ME algorithms can become complex due to irregular data flow. Lack of data reuse in these algorithms leads to the multiple reads of the same data from the external memory and hence more power consumption [3,[11][12][13].…”

“…a 4-bit ripple adder is as fast as a carry select or carry save adder but is smaller), and the reduced bit SAD (RBSAD) calculations are faster and consume less power. The memory will be smaller as well as the input/output (I/O) memory bandwidth [3,[11][12][13][21][22][23][24][25]. A drawback [21][22][23] of this method which was pointed out previously is that the reduced dynamic range, from 8-bit numbers to 4-bit numbers, will generate poorer peak signal to noise ratio (PSNR) values especially for sequences with high spatial and temporal correlations (e.g.…”

Low Active Power High Speed Cache Design

“…As per ITRS projection, embedded cache will occupy 90% of a system on a chip by 2013 [3]. Even today, an H-264 encoder for a highdefinition television requires, at least, a 500 kb memory as a search-window buffer that contributes 40% to its total power consumption [4].…”

Fast Algorithm and Architecture Design of Low-Power Integer Motion Estimation for H.264/AVC

“…For previous H.264/AVC IME designs, several hardware architectures were proposed to support a full search (FS), i.e., exhausted search, algorithm [8]- [12]. They provide good candidate-level DR with regular searching flows, but the computational complexity is large because of the exhausted search.…”