Abstract:This paper presents the fabrication and electrical characterization of superconducting high-aspect ratio through-silicon vias DC-sputtered with aluminum. Fully conformal and void-free coating of 300 μm-deep and 50 μm-wide vias with Al, a CMOS-compatible and widely available superconductor, was made possible by tailoring a funneled sidewall profile for the axisymmetric vias. Single-via electric resistance as low as 80.44 m at room temperature and superconductivity below 1.28 K were measured by a cross-bridge Ke… Show more
“…Various approaches to this have been demonstrated, for example with spring-loaded pogo pins [12,13] and with galvanic bonding of the qubit substrate to a wiring/interposer substrate [14][15][16]. To avoid spurious modes due to slotlines, divided ground planes can be inductively shunted with airbridges [10] or with superconducting through substrate vias (TSVs) [15,17,18]. To avoid low frequency cavity modes, one solution is * peter.leek@physics.ox.ac.uk to divide the quantum processor into subsystems, with each subsystem enclosed in a cavity with dimensions 1 cm [19][20][21][22].…”
We report high qubit coherence as well as low crosstalk and single-qubit gate errors in a superconducting circuit architecture that promises to be tileable to 2D lattices of qubits. The architecture integrates an inductively shunted cavity enclosure into a design featuring non-galvanic out-of-plane control wiring and qubits and resonators fabricated on opposing sides of a substrate. The proofof-principle device features four uncoupled transmon qubits and exhibits average energy relaxation times T1 = 149(38) µs, pure echoed dephasing times T φ,e = 189(34) µs, and single-qubit gate fidelities F = 99.982(4)% as measured by simultaneous randomized benchmarking. The 3D integrated nature of the control wiring means that qubits will remain addressable as the architecture is tiled to form larger qubit lattices. Band structure simulations are used to predict that the tiled enclosure will still provide a clean electromagnetic environment to enclosed qubits at arbitrary scale.
“…Several works in literature have described a variety of approaches to deploy superconducting interposers [6]- [14], including our previous investigations [15], [16]. Foxen et al [7] used indium bumps as electrical interconnects between two planar devices with aluminum wiring.…”
Section: Introductionmentioning
confidence: 99%
“…We have previously demonstrated the fabrication of high aspect-ratio (HAR) superconducting TSVs using sputtered aluminum [15], [16]. Sputter deposition is a physical vapor deposition technique used for the deposition of thin films.…”
This paper describes the microfabrication and electrical characterization of aluminum-coated superconducting through-silicon vias (TSVs) with sharp superconducting transition above 1 K. The sharp superconducting transition was achieved by means of fully conformal and void-free DCsputtering of the TSVs with Al, and is here demonstrated in up to 500 µm-deep vias. Full conformality of Al sputtering was made possible by shaping the vias with a tailored hourglass profile, which allowed a metallic layer as thick as 430 nm to be deposited in the center of the vias. Single-via electric resistance as low as 160 mΩ at room temperature and superconductivity at 1.27 K were measured by a three-dimensional (3D) cross-bridge Kelvin resistor structure. This work establishes a CMOS-compatible fabrication process suitable for arrays of superconducting TSVs and 3D integration of superconducting silicon-based devices.
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