High Coherence in a Tileable 3D Integrated Superconducting Circuit Architecture

Abstract

We report high qubit coherence as well as low crosstalk and single-qubit gate errors in a superconducting circuit architecture that promises to be tileable to 2D lattices of qubits. The architecture integrates an inductively shunted cavity enclosure into a design featuring non-galvanic out-of-plane control wiring and qubits and resonators fabricated on opposing sides of a substrate. The proofof-principle device features four uncoupled transmon qubits and exhibits average energy relaxation times T1 = 149(38) µs, pure echoed dephasing times T φ,e = 189(34) µs, and single-qubit gate fidelities F = 99.982(4)% as measured by simultaneous randomized benchmarking. The 3D integrated nature of the control wiring means that qubits will remain addressable as the architecture is tiled to form larger qubit lattices. Band structure simulations are used to predict that the tiled enclosure will still provide a clean electromagnetic environment to enclosed qubits at arbitrary scale.

Quasiparticles in superconducting qubits with asymmetric junctions

“…is a few kHz [9,10,46]. On the other hand, recent measurements reports Γ ph ranging from 100 Hz down to less than 1 Hz, so that we can assume Γ ph Γ ee 10 and p 1 1.…”

“…According to recent experiments on state-of-the-art transmons [9,33,46,47], the main qubit relaxation mechanism is of non-quasiparticle origin, Γ ee 10 > Γ eo 10 ∼ Γ ph . Indeed, in state-of-the-art qubits, the relaxation time…”

Characterisation of spatial charge sensitivity in a multi-mode superconducting qubit

“…We fabricate device A (B) through electron beam lithography (and photolithography), patterning both sides of a 0.5 mm sapphire (silicon) substrate. Each device is mounted inside an aluminium sample holder within a mu-metal magnetic shield, anchored to the 10 mK stage of a dilution refrigerator, operating with a standard cQED experimental setup [31]. A comparison of the device designs is shown in Appendix B.…”

Toward Realization of Scalable Packaging and Wiring for Large-Scale Superconducting Quantum Computers

“…Throughsilicon vias (TSVs) [26]- [29] are one of the best ways to implement the metallic structure in a chip. Metallic pillar structures made by machining are also useful for this purpose [30]. A similar rectangular cavity mode can also exist in the housing surrounding the chip.…”