Super low-noise self-aligned gate GaAs MESFET with noise figure of 0.87 dB at 12 GHz

Formation of a submicron GaAs MESFET gate using a four-layer dielectric dummy gate

“…One of the cutting edge tech niques enabling one to obtain MESFETs with high per formance is the technique of self aligned device ele ments, particularly, self aligned gate and source and drain contact regions of the transistor [5][6][7][8][9][10][11][12][13][14][15][16][17]. The dis tinctive features of this method are the fact that the res olution of the lithography under use is much higher than the obtained gate length, and that the constitutive operations are performed in the following sequence: Formation of a large sized self aligned element.…”

“…Commercially available self aligned GaAs MMIC technologies can be conventionally divided into two groups. In the first one, a gate based on refractory metallization acts as a self alignment element, which can withstand activation high temperature annealing of an ion implanted layer (IIL) at T ≥ 850°С [5][6][7][8][9]. In the second group, a one , two , or three layer dielectric dummy gate is used as a self aligned element, which, on IIL high temperature annealing and diminishing dummy date length, is replaced by a metal gate [9][10][11][12][13][14][15][16][17].…”