Sudden Power-Outage Resilient In-Processor Checkpointing for Energy-Harvesting Nonvolatile Processors

Onizawa, Naoya; Mochizuki, Ayako; Tamakoshi, Akira; Hanyu, Takahiro

doi:10.1109/tetc.2016.2604083

Cited by 13 publications

(6 citation statements)

References 23 publications

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“…input) voltage, while the voltage detector monitors the power supply voltage and can trigger specific functions when the voltage falls to a predefined threshold. By implementing backup/restore mechanisms triggered by the voltage detector, several checkpointing-based solutions have been proposed to allow for intermittent task execution [10], [21]. For example, an intuitive approach is to checkpoint all volatile data in VM (including registers and main memory) to NVM when the voltage falls below a threshold and then write the data back to VM when power is resumed.…”

Section: A Ultra-lightweight Intermittent Devicesmentioning

confidence: 99%

Enabling Failure-Resilient Intermittent Systems Without Runtime Checkpointing

Chen

Kuo

Hsiu

2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Self-powered intermittent systems typically adopt runtime checkpointing as a means to accumulate computation progress across power cycles and recover system status from power failures. However, existing approaches based on the checkpointing paradigm normally require system suspension and/or logging at runtime. This paper presents a design which overcomes the drawbacks of checkpointing-based approaches, to enable failure-resilient intermittent systems. Our design allows accumulative execution and instant system recovery under frequent power failures while enforcing the serializability of concurrent task execution to improve computation progress and ensuring data consistency without system suspension during runtime, by leveraging the characteristics of data accessed in hybrid memory. We integrated the design into FreeRTOS running on a Texas Instruments device. Experimental results show that our design can still accumulate progress when the power source is too weak for checkpointing-based approaches to make progress, and improves the computation progress by up to 43% under a relatively strong power source, while reducing the recovery time by at least 90%.

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Section: A Ultra-lightweight Intermittent Devicesmentioning

confidence: 99%

Enabling Failure-Resilient Intermittent Systems Without Runtime Checkpointing

Chen

Kuo

Hsiu

2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…If data bits are not correctly restored due to soft errors and=or write errors, the nonvolatile processors cannot continue the operation and hence their initialization is required. 30) Let us define the restore-error rate (RER) of a conventional CMOS=MTJ-based NVFF. As a conventional NVFF is not tolerant to both soft and write errors, it can correctly restore data bits unless both soft and write errors occur.…”

Section: Restore-error Rate In Nvffsmentioning

confidence: 99%

Soft/write-error-resilient CMOS/magnetic tunnel junction nonvolatile flip-flop based on majority-decision shared writing

Onizawa

Hanyu

2017

Jpn. J. Appl. Phys.

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A soft/write-error-resilient nonvolatile flip-flop (NVFF) using three-terminal magnetic tunnel junctions (MTJs) is presented. The proposed NVFF exploits a redundant structure with a majority bit implicitly stored, which is tolerant to soft errors including both single-event transients (SETs) and single-event upsets (SEUs). For write-error resilience, all the bits of the redundant MTJs are written using the majority bit with a shared writecurrent path, exhibiting 1-bit soft-error correction and 1-bit write-error masking. In addition, the shared writing scheme reduces the number of writecurrent paths to one-third of that with a redundant NVFF with 1-bit soft/write-error masking. Using 65 nm CMOS/MTJ technologies, the proposed NVFF achieves a few orders-of-magnitude reduction in the failure in time (FIT), a 31% reduction in the transistor count, and a 65% reduction in the write energy in comparison with the redundant NVFF.

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“…The backup and restore processes are called checkpointing. [9][10][11][12] Traditionally, data are backed up to external storages, such as HDD and SSD, causing slow backup and restoring. In Ref.…”

Section: Continuous Operations For Energy-harvesting Applicationsmentioning

confidence: 99%

“…To solve the consistency issue, the nonvolatile processor (Type II) exploits the dualredundant NVFFs and the consistency adjuster for continuous operations. 12) To evaluate the performance of the volatile and nonvolatile computer systems in energy-harvesting applications discussed in this section, the energy dissipations are modeled in the next section. In energy-harvesting applications, the total amount of energy produced from the energy-harvesting sources is almost unlimited, but operations need to be complete within specific time periods.…”

Section: Reinitialization Processes Due To Power Failuresmentioning

confidence: 99%

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Evaluation of reinitialization-free nonvolatile computer systems for energy-harvesting Internet of things applications

Onizawa

Tamakoshi

Hanyu

2017

Jpn. J. Appl. Phys.

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In this paper, reinitialization-free nonvolatile computer systems are designed and evaluated for energy-harvesting Internet of things (IoT) applications. In energy-harvesting applications, as power supplies generated from renewable power sources cause frequent power failures, data processed need to be backed up when power failures occur. Unless data are safely backed up before power supplies diminish, reinitialization processes are required when power supplies are recovered, which results in low energy efficiencies and slow operations. Using nonvolatile devices in processors and memories can realize a faster backup than a conventional volatile computer system, leading to a higher energy efficiency. To evaluate the energy efficiency upon frequent power failures, typical computer systems including processors and memories are designed using 90 nm CMOS or CMOS/magnetic tunnel junction (MTJ) technologies. Nonvolatile ARM Cortex-M0 processors with 4 kB MRAMs are evaluated using a typical computing benchmark program, Dhrystone, which shows a few order-of-magnitude reductions in energy in comparison with a volatile processor with SRAM.

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Sudden Power-Outage Resilient In-Processor Checkpointing for Energy-Harvesting Nonvolatile Processors

Cited by 13 publications

References 23 publications

Enabling Failure-Resilient Intermittent Systems Without Runtime Checkpointing

Enabling Failure-Resilient Intermittent Systems Without Runtime Checkpointing

Soft/write-error-resilient CMOS/magnetic tunnel junction nonvolatile flip-flop based on majority-decision shared writing

Evaluation of reinitialization-free nonvolatile computer systems for energy-harvesting Internet of things applications

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