2017
DOI: 10.1039/c7nr00088j
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Subthreshold swing improvement in MoS2 transistors by the negative-capacitance effect in a ferroelectric Al-doped-HfO2/HfO2 gate dielectric stack

Abstract: Obtaining a subthreshold swing (SS) below the thermionic limit of 60 mV dec by exploiting the negative-capacitance (NC) effect in ferroelectric (FE) materials is a novel effective technique to allow the reduction of the supply voltage and power consumption in field effect transistors (FETs). At the same time, two-dimensional layered semiconductors, such as molybdenum disulfide (MoS), have been shown to be promising candidates to replace silicon MOSFETs in sub-5 nm-channel technology nodes. In this paper, we de… Show more

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Cited by 126 publications
(65 citation statements)
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“…The fact that the ferroelectric material can exhibit such a state of negative capacitance has already been demonstrated. 3,4,[6][7][8][9][10][11][12][13][14][15][16][17][18] Therefore, if another dielectric capacitor is placed in series with the ferroelectric [as shown schematically in Fig. 1(b)], a voltage amplification is expected across the dielectric capacitor.…”
mentioning
confidence: 99%
“…The fact that the ferroelectric material can exhibit such a state of negative capacitance has already been demonstrated. 3,4,[6][7][8][9][10][11][12][13][14][15][16][17][18] Therefore, if another dielectric capacitor is placed in series with the ferroelectric [as shown schematically in Fig. 1(b)], a voltage amplification is expected across the dielectric capacitor.…”
mentioning
confidence: 99%
“…Atomically thin layers of two dimensional (2D) semiconductors are considered as highly promising materials for field‐effect transistor (FET) channels because the van der Waals character of bonding allows fabrication of mismatch‐free heterojunction stacks . Furthermore, the expected reduced density of mismatch‐induced coordination defects and suppression of short channel effects potentially enable efficient device downscaling additionally profiting from bandgap engineering by simple adjustment of the 2D channel thickness . However, the few‐monolayer (ML) thick channel mandates tight control of the electric field at the surface of the 2D semiconductor, particularly if targeting devices with steep sub‐threshold slope for low‐power applications such as tunnel FETs .…”
Section: Introductionmentioning
confidence: 99%
“…Howerver, states at the monolayer/trilayer interface is not negligible, which are detrimental to the on/off ratio. SS can be reduced by fabricating an FET with a thin high‐κ dielectric film or changing a passive gate insulator to an active one, use an electrochemical gate or exploiting the negative‐capacitance effect in ferroelectric (FE) materials …”
Section: Summary Of Calculated Interface Distance D Average Electronmentioning
confidence: 99%
“…SS can be reduced by fabricating an FET with a thin high-κ dielectric film or changing a passive gate insulator to an active one, [26] use an electrochemical gate [27] or exploiting the negative-capacitance effect in ferroelectric (FE) materials. [28] Finally we discuss the on-state current which is often a problem for 2D FET due to the thin atomic monolayer of the channel. The computed on-current of hydrogenpassivated structure is 611.8 μA μm À1 , which has a remar kable increase comparing with 102 μA μm À1 for unpassivated condition.…”
mentioning
confidence: 99%