Subthreshold Analog/RF Performance Enhancement of Underlap DG FETs With High- $k$ Spacer for Low Power Applications

Performance optimization of nanoscale junctionless transistors through varying device design parameters for ultra-low power logic applications

“…may be used as sidewall spacer layers in nanoscale MOSFETs as they have pretty high dielectric constant, acceptable amount of conduction and valence band offsets with Si and also are thermodynamically stable with Si [9,10]. There have been many reports regarding the impact of various single high-k sidewall spacer layers on the logic and analog/RF performance of MOSFETs [5,8,11,12]. The source/drain resistance plays an important role in determining the characteristics of MOSFETs particularly at the nanodecameter technology nodes.…”

A new T-Shaped Source/Drain Extension (T-SSDE) Gate Underlap GAA MOSFET with enhanced subthreshold analog/RF performance for low power applications

“…2(b) shows the variation of electric field for both the devices with position along the channel. It clearly shows that the electric 0. field is larger near the source side which eventually increases the average drift velocity of the electron in the channel, there by increasing the carrier transport efficiency [12][13][14]. Further, due to the electric field reduction at drain end the hot carrier effect is also suppressed in T-SSDE Gate Underlap GAA MOSFET.…”

Analysis of High-<inline-formula> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula> Spacer Asymmetric Underlap DG-MOSFET for SOC Application

“…Now again, on increasing the spacer k under superthreshold bias, the Q s remains unaffected while Q d increases, this reduces the Q s − Q d factor in (1). Then again, high-k spacer significantly improve the μ in the underlap region [18], thereby slightly increasing the g m .…”