Performance optimization of nanoscale junctionless transistors through varying device design parameters for ultra-low power logic applications

Effects of asymmetric underlap spacers on nanoscale junctionless transistors and design of optimised CMOS amplifiers

“…Thus, for all symmetric and asymmetric devices, with the increase in spacer dielectric constant the parasitic S/D resistance in the underlap region decreases due to the stronger accumulation of carriers in that region leading to an enhanced I ON and also the slope of the I D −V GS curve observed in terms of increased transconductance. These results are consistent with earlier findings [16, 18]. Hence, we can establish that with increasing k , g dsat increases for a device having L D > L S , whereas it reduces for a device with L D < L S .…”

“…are usually used as gate insulators and sidewall spacer layers in nanoscale metal-oxidesemiconductor FETs (MOSFETs) because of their high dielectric constant, considerable amount of conduction and valence band offsets with silicon (Si), apart from their thermodynamic stability with Si [11,12]. There have been numerous published works regarding effects of spacer layers on the analogue/RF and digital circuit performance of inversion-mode (IM) [13][14][15] as well as JCTs [16][17][18][19]. Extensive investigations are reported concerning the impact of dual-k spacers on multiple application domains such as analogue, logic and memory circuit performances of IM FinFETs [20][21][22][23] including a recently coined new device architecture, e.g.…”

“…a reconfigurable FET [24]. The influences of underlap spacer layers in improving low‐power logic applications for double‐gate JLTs, and also for FinFETs were reported in [18, 19, 25]. Additionally, the enhanced analogue performance of double‐gate JCTs using spacer engineering was investigated in [26, 27].…”

Влияние формы канала на амплитуду случайных телеграфных шумов в подпороговой области беспереходного FinFET-транзистора

“…Короткоканальные эффекты в JL FinFET-транзисторах изучаются довольно широко [6][7][8], в то время как исследования влияния единичных оксидных или граничных ловушечных зарядов, вызывающих СТШ-сигналы в этих транзисторах, на ток стока, а также работы, связанные с применением этих транзисторов в логике ультранизкой мощности, находятся на начальной стадии. Есть работы, в которых основное внимание уделяется зависимости амплитуды СТШ-сигнала от технологии изготовления транзистора, температуры, напряжения на затворе и стоке в режиме аккумуляции [9,10], зависимости показателей эффективности работы беспереходного транзистора в логике ультранизкой мощности от уровня легирования канала, диэлектрической постоянной материала спейсера, сопротивления канала [11]. Однако имеется очень мало работ, в которых исследуется влияние технологических флуктуаций геометрических размеров и отклонений от предполагаемых форм при изготовлении наноразмерных JL FinFET-транзисторов на их шумовые характеристики.…”

Amplitude of Random Telegraph Noise in Junctionless FinFET with Different Channel Shape

“…While the short channel effects in the JL-FinFET were thoroughly investigated [2−4], issues related to the influence of single oxide-or interface-trapped charges on both the drain current and induced random telegraph noise (RTN) signals in transistors [5] are studied to a much lesser extent. Some previous studies have focused on the dependence of RTN amplitude on the transistor manufacturing technology, temperature, gate and drain voltages in accumulation mode [6,7], and the dependence of JL FinFET operating efficiency in ultra-low power logic on the level of channel doping, the dielectric constant of the spacer and the channel resistance [8]. To the best of our knowledge, very few papers have reported on the influence of technological factors such as variations in geometric parameters and deviations from preset shapes of nano-sized JL FinFETs on their noise properties.…”