Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting
DOI: 10.1109/bipol.2002.1042878
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Substrate options and add-on process modules for monolithic RF silicon technology

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Cited by 21 publications
(11 citation statements)
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“…Any of those steps should preferably be arranged as a modular addition to the core device integration process [30]. Standard silicon wafer material, grown by using the Czochralski technique, is still limited to resistivities below 100 cm [31], but the recently introduced magnetic Czochralski wafers may allow for resistivities up to 1 k cm [32].…”
Section: Optimization Guidelinesmentioning
confidence: 99%
“…Any of those steps should preferably be arranged as a modular addition to the core device integration process [30]. Standard silicon wafer material, grown by using the Czochralski technique, is still limited to resistivities below 100 cm [31], but the recently introduced magnetic Czochralski wafers may allow for resistivities up to 1 k cm [32].…”
Section: Optimization Guidelinesmentioning
confidence: 99%
“…This, however, brings several technological issues in focus that may form bottlenecks, in particular the considerable losses in the conventional silicon substrates [6]. Currently, resistivities of at most [10][11][12][13][14][15][16][17][18][19][20] cm [low-resistivitysilicon(LRS)]arebeingused.Thiscorrespondsto conductivities that lead to considerable substrate losses and, thus, to excessive attenuation of integrated transmission lines [7] and reduced quality factors of on-chip inductors [8].…”
mentioning
confidence: 99%
“…Furthermore, the surface-channel losses can be bias-dependent, leading to difficulties in parameter control [7]. The impact of a parasitic surface channel is consequently more pronounced in coplanar wave guide (CPW) structures, in which the electric field is more concentrated at the wafer surface, [6]- [9], [11] than in microstrip structures [7], [10], or spiral inductors [12]. In view of the recent attention to the application of HRS substrates in RFIC processes [13], elimination of surface channels on HRS is highly desirable.…”
Section: Introductionmentioning
confidence: 99%
“…H IGH-RESISTIVITY SILICON (HRS) has long been viewed as an ideal substrate for radio frequency integrated circuits (RFICs) [1]- [5], but surface effects tend to overshadow the potentially low RF loss levels in HRS [6]- [9]. Charges within the insulating SiO layer and at the SiO interface lead to accumulation or inversion layers at the silicon surface, contributing to an increased attenuation of integrated transmission lines [6]- [11], a reduced quality factor (Q) of on-chip spiral inductors [12], and a leakage path between integrated devices [6].…”
Section: Introductionmentioning
confidence: 99%