Substrate Engineering Concepts to Mitigate Charge Collection in Deep Trench Isolation Technologies

A review of ion beam induced charge microscopy

“…Unfortunately, they are quite sensitive to SEUs. In order to study this sensitivity, IBIC experiments were carried out for several devices and TCAD model calculations performed [107][108][109][110][111]. Here only the IBIC results for a particular device are shown.…”

Resilient computer system design

“…using epitaxial substrate doping (EPI layer charge reduction) (Puchner et al 2006), wells (single well, twin well and triple well processes) (Pellish et al 2006;Puchner et al 2006;Roche and Gasiot 2005), buried layers (Roche and Gasiot 2005) and dry thermal oxidation (Hughes and Benedetto 2003) -Non-capacitance techniques, e.g. increasing the node coupling capacitance between storage nodes and memory, or using a DRAM capacitor on top of the memory cell (Geppert 2004) -Using alternative insulating substrates, e.g.…”

Signal noise perturbation on automotive mixed-mode semiconductor device generated by graded substrate defect

“…More specifically, when the injected minority carrier current ranges from several tens of mAmps to several Amps such that the injected minority carriers into the substrate create a conductivity modulation in the substrate and the carrier lifetime is governed by high-level lifetime. That is why, it is classically used in recent technologies some typical structures (such as buried layers, isolation trench, SOI) [5][6][7], in order to isolate the different type of device cohabitant in a same component. In order to explain the noise generation from power device to digital device from other blocks, this study suggested that isolation trenches with P++ substrate were not sufficient (P++ in Fig.…”