Subnanosecond Self-Aligned I/sup 2/L/MTL Circuits

Tang, D.D.; Ning, T.H.; Isaac, R.; Feth, G. C.; Wiedmann, S.K.; Yu, Hsing-Tse

doi:10.1109/jssc.1980.1051419

Cited by 10 publications

(5 citation statements)

References 20 publications

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“…As a result, the critical depletion capacitors in the SF-I L gate are smaller than those in the C-I L gate. Even further benefits would be obtained if self-aligned fabrication schemes were used to reduce depletion charge and eliminate the excess charge associated with the extrinsic base rails [4]. Such a strategy has achieved a switching time of 290 ps in a pure Si I L gate [14] at a gate geometry of 3 m and one for SiGe I L is presented in the next section.…”

Section: Discussionmentioning

confidence: 99%

“…2 and 3. The principle is demonstrated by consideration of the following two equations which describe the switched (free) charge associated with a quasi-neutral region bounded by injecting and collecting junctions: (4) and that for the switched charge associated with a depletion region (5) where electronic charge; area; intrinsic carrier concentration of the semiconductor; doping concentration of the region; thickness of the epitaxial layer (or the diffusion length if necessary); applied junction voltage; built-in junction voltage; thermal voltage. The voltage terms in expressions (4) and (5) account for the difference in junction voltage at logic "1" and logic "0" and are defined as:…”

Section: The Charge Control Modelmentioning

confidence: 99%

“…The self-aligned Si I L structure of Tang et al [4] was implemented in the model to provide experimental validation of the analysis method. Average values for impurity levels of diffused regions were used, deduced from the sheet resistance values given and taking into account doping dependence of mobility based on the average values.…”

Section: A Validation Of the Modeling Techniquementioning

confidence: 99%

“…The minimum gate delay of Si I L [3] is primarily determined by stored charge in parasitic diodes associated with the extrinsic base regions of the I L gate. Self-aligned collector-base structures have been reported [4] which minimize the area of these parasitic diodes and deliver a gate delay of 0.8 ns for a layout geometry of 2.5 m and a fan-out of 3. Other parasitics that can influence the gate delay are series resistance effects in the base and charge storage in the intrinsic base of the pnp transistor.…”

Section: Introductionmentioning

confidence: 99%

“…Validation of the charge storage model by a comparison of the predicted switching time as a function of injection current with the measured results of Tang et al[4].…”

mentioning

confidence: 99%

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Analysis of Si:Ge heterojunction integrated injection logic (I/sup 2/L) structures using a stored charge model

Wainwright

Hall

Ashburn

et al. 1998

IEEE Trans. Electron Devices

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A quasi-two-dimensional stored charge model is developed as an aid to the optimization of SiGe integrated injection logic (I 2 L) circuits. The model is structure-based and partitions the stored charge between the different regions of the I 2 L gate. Both the NpN switching transistor and the PNp load transistor are correctly modeled and the effects of series resistances on the gate operation are taken into account. The model is applied to surface-fed and substrate-fed variants of SiGe I 2 L and the Ge and doping concentrations varied to determine the important tradeoffs in the gate design. At low injector currents, the substrate-fed variant is found to be faster because of lower values of critical depletion capacitances. At high injector currents, the performance of both variants is limited by series resistances, particularly in the NpN emitter layer. The inclusion of 16% Ge in the substrate-fed I 2 L gate leads to a decrease in the dominant stored charge by a factor of more than ten, which suggests that gate delays well below 100 ps should be achievable in SiGe I 2 L even at a geometry of 3 m. The model is applied to a realistic, self-aligned structure and a delay of 34 ps is predicted. It is expected that this performance can be improved with a fully optimized, scaled structure. NOMENCLATURE N-type Si doping concentration in the substrate (used exclusively in C-I L). N-type Si doping concentration in the switch emitter (used exclusively in C-I L). N-type Si doping concentration in the injector base

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Section: Discussionmentioning

confidence: 99%

Section: The Charge Control Modelmentioning

confidence: 99%

Section: A Validation Of the Modeling Techniquementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…Validation of the charge storage model by a comparison of the predicted switching time as a function of injection current with the measured results of Tang et al[4].…”

mentioning

confidence: 99%

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