Organic thin-film transistors (OTFT) processed at low-temperatures offer prospects for a vast number of integrated circuit applications in mechanically flexible, inexpensive, large-area and biomedical electronics [1]. In addition, the low-voltage operation capability of recent OTFTs makes them well-suited for battery-powered or radio frequency-coupled portable devices [2]. In such applications, data conversion to interface the digital processors with the analog world is an essential necessity. Here, we demonstrate a compact 6b current-steering D/A converter (DAC) circuit, built in OTFT technology, which is 1000× faster and 30× smaller than the previously published data for a 6b DAC [3]. These considerable improvements result from an OTFT fabrication process based on silicon stencil masks that provide submicron channel length capability and excellent transistor matching [4], [5].DACs can be classified into three main classes, namely resistive-based, capacitive-based and current-steering architectures. By comparing the three classes, the current-steering architecture is known to be superior in speed and compactness. However, excellent device matching is required for achieving a linear transfer characteristic of the DAC. Since OTFT fabrication processes so far have been prone to large device-to-device variations, the first approach to OTFT DACs used a switched-capacitor architecture (C-2C DAC), which is less sensitive to the poor transistor matching [3]. However, it has recently been reported in [4][5] that ntype and p-type top-contact OTFTs fabricated by using silicon stencil masks allow for submicron channel lengths and provide much improved transistor matching compared to devices fabricated with conventional shadow masks. This stencil mask-based fabrication process allows for designing current-steering DACs at considerably higher sample rate and smaller chip area consumption.The schematic diagram of the 6b current-steering DAC is shown in Fig. 18.2.1. The converter consists of three main blocks: a current-source array (CSA) that contains binary-weighted current sources and an input current mirror, a switch array (SWA) that contains binary-weighted switches, and a linear current-tovoltage converter (CVC) at the output. The binary current-steering architecture is employed because of its lower complexity, smaller area and lower power dissipation compared to the unary current-steering architecture. This type of currentsteering can be designed by exclusively using either n-type or p-type transistors, thus not requiring complementary OTFT technology. According to [3], the operational speed of the p-type OTFTs is approximately 10× higher than that of their n-type counterparts. This is mainly due to the higher carrier mobility in the ptype OTFT channel regions (μ p ≈ 10μ n ). For this reason, the 6b DAC is designed in p-type OTFT technology.Referring to Fig. 18.2.1, strict requirements apply to the floorplan and the layout due to the large number of current sources that lead to complex routing. There are mainly two appro...