Submicrometer Ultralow-Power TFT With 1.8 nm NAOS $ \hbox{SiO}_{2}/\hbox{20} \ \hbox{nm}$ CVD $\hbox{SiO}_{2}$ Gate Stack Structure

Kubota, Yasushi; Matsumoto, Tetsuya; Imai, Shigeki; Yamada, Misuzu; Tsuji, Hiroshi; Taniguchi, Kenji; Terakawa, Susumu; Kobayashi, Hikaru

doi:10.1109/ted.2011.2108657

Cited by 10 publications

(13 citation statements)

References 41 publications

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“…The high-quality SiO 2 growth on Si substrates has conventionally been possible through thermal oxidation under high temperatures over 900 °C. Other conventional deposition techniques that have been developed for the formation of SiO 2 films include thermal chemical vapor deposition (CVD) and plasma-enhanced CVD. − However, such high temperatures and damage-inducing processes limit the versatility of SiO 2 , particularly for back-end interconnects and thermally delicate substrates with strict temperature constraints, such as polymers. Further, with the ongoing demand for complex and three-dimensional (3D) structures in advanced device architectures, there is a strong requirement for the deposition of ultrathin and conformal SiO 2 films .…”

Section: Introductionmentioning

confidence: 99%

Thermal Atomic Layer Deposition of Device-Quality SiO₂ Thin Films under 100 °C Using an Aminodisilane Precursor

Kim

Lee

Jeong³

et al. 2019

Chem. Mater.

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SiO2 is one of the most important dielectric materials that is widely used in the microelectronics industry, but its growth or deposition requires high thermal budgets. Herein, we report a low-temperature thermal atomic layer deposition (ALD) process to fabricate SiO2 thin films using a novel aminodisilane precursor with a Si–Si bond, 1,2-bis(diisopropylamino)disilane (BDIPADS), together with ozone. To compare the film quality, ALD SiO2 films grown at various temperatures from 250 down to 50 °C were systematically investigated. Our data suggest that even without the aid of plasma-enhanced or catalyzed surface reactions, high-quality SiO2 films with relatively high growth rates, high film densities, and low impurity contents compared to conventional Si precursors can be attained through our process at a low growth temperature (∼50 °C). Chemical analyses via Auger electron spectroscopy, Fourier transform infrared spectroscopy, and X-ray photoelectron spectroscopy confirm the formation of stoichiometric SiO2 films without noticeable impurity contents of nitrogen and carbon, regardless of the growth temperature. However, low-temperature growth of the SiO2 film (≤80 °C) results in a slight ingress of SiH-related moieties during the ALD processes that is not observed at temperatures over 80 °C. Density functional theory calculations show that the Si–Si bond present in the BDIPADS precursor is easier to be oxidized compared to the Si–H bonds. Through electrical characterization of the SiO2 films grown at different temperatures, we confirm only slight degradation in the dielectric constants, leakage currents, and breakdown fields with decreasing growth temperature, which may be due to the slightly decreased film density and the increased defect density of SiH-related bonds.

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Section: Introductionmentioning

confidence: 99%

Thermal Atomic Layer Deposition of Device-Quality SiO₂ Thin Films under 100 °C Using an Aminodisilane Precursor

Kim

Lee

Jeong³

et al. 2019

Chem. Mater.

View full text Add to dashboard Cite

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“…Properly manufactured SiO 2 thin layers exhibit excellent physical and chemical properties, such as optical transparency, chemical inertness, scratch resistance, and hardness . The films can be conventionally deposited on a selected substrate through a variety of techniques, such as chemical vapor deposition (CVD), , plasma-enhanced CVD (PECVD), − and so on. As the demand to decrease device sizes continues, the temperature range suitable for thin-film fabrications has become very narrow, and a low-temperature process for SiO 2 deposition is required to ensure excellent device integrity and performance. , Although PECVD can produce SiO 2 films at a relatively low temperature (<300 °C), the substrate could be damaged by the use of plasma, and the generated surface impurities could become detrimental to the film quality .…”

Section: Introductionmentioning

confidence: 99%

On the Mechanisms of SiO₂ Thin-Film Growth by the Full Atomic Layer Deposition Process Using Bis(t-butylamino)silane on the Hydroxylated SiO₂(001) Surface

Han

Zhang

et al. 2011

J. Phys. Chem. C

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“…20,27 Moreover, the characteristics of the CVD SiO 2 overlayer are thought to be improved by the NAOS interfacial layer with a better CVD SiO 2 nucleation on a NAOS layer compared to a poly-Si surface. This is because the NAOS treatment greatly decreased the concentrations of metal contaminants (e.g., Fe contaminant before and after the NAOS treatment: ∼4 × 10 10 and ∼1 × 10 10 atoms/cm 2 , respectively) and formed considerably flat SiO 2 surfaces (cf.…”

Section: Resultsmentioning

confidence: 99%

Ultra-Low Power Poly-Si TFTs with 10 nm Stacked Gate Oxide Fabricated by Nitric Acid Oxidation of Silicon (NAOS) Method

Matsumoto

Tsuji

Terakawa

et al. 2015

ECS J. Solid State Sci. Technol.

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We have fabricated poly-silicon-based thin film transistors (TFTs) on glass substrates, and achieved ultra-low power consumption by driving at 1 V. The gate oxide layer has a 10 nm thick stacked structure with a 1.4 nm interfacial SiO 2 layer formed by the nitric acid oxidation of silicon (NAOS) method and a 8.6 nm SiO 2 layer formed by a plasma-enhanced chemical vapor deposition (PECVD) method. The dynamic power consumption ratio of the NAOS-TFTs is 1/144 of that for the currently commercial TFTs with the driving voltage of 12 V and 80 nm gate oxide. The off-current decreases by ∼2 orders of magnitude by insertion of the ultra-thin NAOS SiO 2 layer. The off-current decrease is attributed to i) blocking of the gate leakage current by the NAOS SiO 2 layer, and ii) improvement of the quality of the deposited oxide on the NAOS SiO 2 layer because of better nucleation, and consequently, the high on/off ration exceeding 10 9 is achieved. Low power consumption is one of the most important issues for mobile products with batteries. System liquid crystal displays (LCDs) are widely used for popular mobile electronic products such as smart phones, e-books, and personal digital assistance (PDAs) because of their low power consumption.The dynamic consumed power of a TFT, P, is expressed aswhere f is a signal frequency, C is a charging and discharging capacitance, and V is a driving voltage. Therefore, the consumed power can be decreased most effectively by reducing the driving voltage, which is approximately proportional to a gate oxide thickness. The decrease in the gate insulator thickness makes it possible not only to decrease the consumed power but also to miniaturize TFTs, which greatly improves electrical characteristics of TFTs. 2Thermal oxidation is unavailable for TFT production because of the use of glass substrates with low softening temperature of ∼500• C. Consequently, a gate oxide layer in poly-crystalline Si (poly-Si)-based TFTs is usually formed by the plasma-enhanced chemical vapor deposition (PECVD) method using tetraethyl orthosilicate (TEOS). [3][4][5][6] However, deposition methods have following demerits: i) interface state densities are high due to incomplete interfacial chemical bonds and presence of contaminants before deposition, 7,8 ii) bulk characteristics are poor due to imperfect structure including small SiO 2 particles which were originally formed in the gas phase and C and OH contaminants, 9,10 and due to poor nucleation of an SiO 2 layer on polySi surfaces compared to that on oxide surfaces, iii) the oxide layer thickness is not uniform on rough poly-Si surfaces due to formation of ridge structure arising from laser annealing of amorphous-Si (a-Si) films to crystallize. 11Extensive studies have been performed for developing direct Si oxidation methods at low temperatures including plasma oxidation, 12,13 photo-oxidation, 14,15 ozone oxidation, 16,17 metalpromoted oxidation, 18,19 etc. We have developed a low temperature direct Si oxidation method, i.e., the chemical oxidation method called ...

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Submicrometer Ultralow-Power TFT With 1.8 nm NAOS $ \hbox{SiO}_{2}/\hbox{20} \ \hbox{nm}$ CVD $\hbox{SiO}_{2}$ Gate Stack Structure

Cited by 10 publications

References 41 publications

Thermal Atomic Layer Deposition of Device-Quality SiO₂ Thin Films under 100 °C Using an Aminodisilane Precursor

Thermal Atomic Layer Deposition of Device-Quality SiO₂ Thin Films under 100 °C Using an Aminodisilane Precursor

On the Mechanisms of SiO₂ Thin-Film Growth by the Full Atomic Layer Deposition Process Using Bis(t-butylamino)silane on the Hydroxylated SiO₂(001) Surface

Ultra-Low Power Poly-Si TFTs with 10 nm Stacked Gate Oxide Fabricated by Nitric Acid Oxidation of Silicon (NAOS) Method

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Submicrometer Ultralow-Power TFT With 1.8 nm NAOS $ \hbox{SiO}_{2}/\hbox{20} \ \hbox{nm}$ CVD $\hbox{SiO}_{2}$ Gate Stack Structure

Cited by 10 publications

References 41 publications

Thermal Atomic Layer Deposition of Device-Quality SiO2 Thin Films under 100 °C Using an Aminodisilane Precursor

Thermal Atomic Layer Deposition of Device-Quality SiO2 Thin Films under 100 °C Using an Aminodisilane Precursor

On the Mechanisms of SiO2 Thin-Film Growth by the Full Atomic Layer Deposition Process Using Bis(t-butylamino)silane on the Hydroxylated SiO2(001) Surface

Ultra-Low Power Poly-Si TFTs with 10 nm Stacked Gate Oxide Fabricated by Nitric Acid Oxidation of Silicon (NAOS) Method

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Thermal Atomic Layer Deposition of Device-Quality SiO₂ Thin Films under 100 °C Using an Aminodisilane Precursor

Thermal Atomic Layer Deposition of Device-Quality SiO₂ Thin Films under 100 °C Using an Aminodisilane Precursor

On the Mechanisms of SiO₂ Thin-Film Growth by the Full Atomic Layer Deposition Process Using Bis(t-butylamino)silane on the Hydroxylated SiO₂(001) Surface