Sub-clock power-gating technique for minimising leakage power during active mode

Abstract

Abstract-This paper presents a new technique, called subclock power gating, for reducing leakage power in digital circuits. The proposed technique works concurrently with voltage and frequency scaling and power reduction is achieved by power gating within the clock cycle during active mode unlike traditional power gating which is applied during idle mode. The proposed technique can be implemented using standard EDA tools with simple modifications to the standard power gating design flow. Using a 90nm technology library, the technique is validated using two case studies: 16-bit parallel multiplier and ARM Cortex-M0 TM microprocessor, provided by our industrial project partner. Compared to designs without sub-clock power gating, in a given power budget, we show that leakage power saved allows 45x and 2.5x improvements in energy efficiency in the case of multiplier and microprocessor, respectively.

Active Mode Subclock Power Gating

“…For experimental comparisons, three modes of operation were implemented in the Cortex-M0: the proposed SCPG with symmetric virtual rail clamping, no power gating enforced using the nOverride signal in Fig. 4, and SCPG with complete shut down [19] achieved by disabling the Ret & nRet transistors shown in Fig. 4.…”

“…14. Measured V V dd charge-up and evaluation time in sub-clock power gating with shut down power gating [19] combinational logic is brought out of shut down and reevaluates which opposes the recharging of V V dd [12]. This droop subsequently slows the combinational re-evaluation, exacerbating the length of T eval to 4µs as shown.…”

“…13. Measured V V dd and V Vss behaviour in sub-clock power gating with shut down power gating [19] VV ss VV dd T pgstart + T eval = 4µs…”

“…Table I showed that the wake-up energy associated with shut down power gating was higher than the proposed symmetric virtual rail clamping circuit through ring oscillator simulations. To compare sub-clock power gating with shut down power gating [19] and the proposed symmetric virtual rail clamping, both techniques have been compared across a range of clock frequencies. Fig.…”

Carry select adder with sub-block power gating for reducing active-mode leakage in sub-32-nm VLSIs

“…However, the proposed sub-block AMPG can be very useful in frequency scaling applications [5]. For example, an ARM Cortex-M0 chip targeted for very low power applications is known to consume 0.9 mW with a supply voltage of 0.6 V using a 90 nm technology library, but a typical power budget can be between tens and hundreds of μWs [6].…”