Abstract:In this paper, we propose a reconfigurable charge pump (RCP) circuit that could change its architecture according to sunlight variation. In strong sunlight, the RCP works by the parallel mode that can maximize the output current. In moderate sunlight, the RCP changes to the serial-parallel mode. When sunlight becomes weak, the RCP runs by the serial mode to keep its output voltage around the target voltage. Compared with the fixed-mode circuit that maintains the serial mode all the time regardless of sunlight variation, the RCP can generate 2.5 times larger output current and has power efficiency better by 24%, in strong sunlight. The area penalty and overhead in power efficiency of the RCP are only 15.8% and 1.2%.
Abstract:In this paper, a new compact but efficient Maximum Power Point Tracking (MPPT) circuit is added to the conventional battery charger. The battery charging is composed of two steps of the Constant Current (CC) charging and Constant Voltage (CV) charging. Unlike the conventional CC charging, the new MPPT circuit can adjust the charging current according to the sunlight intensity to deliver the largest available solar energy to the battery. For the CV, the proposed battery charger can keep its charging voltage on the full charge level thus it does not lose the battery capacity due to the undercharging. The new battery charger can deliver more power to the battery than the charger without MPPT by 98.8%. Also, the charging time can be shortened by 52.3% with 10.5% of layout overhead.
Abstract:In this paper, we have compared three power gating (PG) schemes which are Single-Footer PG (SFPG), Charge-Recycled PG (CRPG), and Dual-Switch PG (DSPG), respectively, in terms of energy loss, crossover time, and wake-up time using the 45-nm Predictive Technology Model. Though the DSPG has been rarely used so far compared to the SFPG and CRPG, the comparison results tell us that the DSPG should be revisited. With the constraint of the same active speed, the DSPG shows higher energy-efficiency and faster wake-up than the others. Based on these results, the DSPG can be regarded as the most suitable PG scheme for reducing leakage and achieving fast wake-up in the future leakage-dominant VLSIs.
Abstract:In this paper, we propose the sub-block Active-Mode Power Gating (AMPG) scheme to reduce the active-mode leakage and apply it to the 32-bit Carry Select Adder (CSA), where the sub-blocks are activated and deactivated according to the idleness during the active time. By doing so, we can reduce the active-mode energy by 21% at the cycle time of 10 ns for the 22-nm node compared to the conventional AMPG. The critical path delay is degraded as little as 1% in the sub-block AMPG. For a given power budget as small as 100 μW, the new sub-block AMPG with 32-nm node can run faster by 47% than the conventional AMPG. Keywords: low-leakage, power gating, sleep transistor, active-mode power gating, run-time power gating Classification: Integrated circuits
References
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