Sub-5-nm Monolayer GaSe MOSFET with Ultralow Subthreshold Swing and High On -State Current: Dielectric Layer Effects

p-Type High-Performance WSi2N4 MOSFETs with the Ultrashort Scale of Sub-5 nm

“…, where Q on (Q off ) is the total charge in the center region of the on (off) state, and W is the channel width. 44 Smaller τ values indicate faster transistor switching. The calculated τ values for sub-5 nm p-and n-type WSi 2 N 4 transistors are given in Tables S2 and S3, respectively.…”

“…The two other key quality factors for evaluating logic transistors are the intrinsic delay time (τ) and PDP. The intrinsic delay time τ = ( Q on – Q off ) W –1 I on –1 , where Q on ( Q off ) is the total charge in the center region of the on (off) state, and W is the channel width . Smaller τ values indicate faster transistor switching.…”

“…Experimental and theoretical studies have shown that the use of high -k dielectric layers can suppress leakage currents, which in turn improves the transport properties of FETs. ,, Here, the I–V g curves of sub-5 nm p- and n- type WSi 2 N 4 MOSFETs without underlap region are investigated using HfO 2 (ε = 25) as the gate dielectric layer in Figure S2. Compared with the case of SiO 2 (ε = 3.9) dielectric layer, the use of high -k dielectric layer can significantly enhance the electrostatic gate control capability of the device, regardless of the p- or n- type WSi 2 N 4 MOSFETs.…”

Promising ultra-short channel transistors based on OM2S (M = Ga, In) monolayers for high performance and low power consumption

“…Group-III chalcogenides possess remarkable electrical and optical features, which can be broadly used in field-effect transistors (FETs), photodetectors and gas sensors. 9–13 For example, the responsivity and on/off ratio of back-gated GaS-based FETs are ∼6.4 A W −1 and ∼170, respectively. 14 The carrier mobilities of atomically thin InSe were discovered to outnumber 10 3 cm 2 V −1 s −1 (at room temperature) and 10 4 cm 2 V −1 s −1 (at liquid-helium temperature), respectively.…”

Anisotropic Low Schottky Barrier and Transport Properties of the Co-Intercalated Bilayer SnS2/Monolayer SnS2 Junction from First Principles

“…With the further miniaturization of the electronic device down to sub-10 nm, , 2D layered materials have become promising candidates for complementing conventional electronics. , Applying them to device utilization can overcome the short-channel effect in Si-CMOS-FET. But FETs based on 2D layered materials encounter the tricky high contact resistance problem, which comes from the surface of 2D materials without dangling bonds and makes it difficult to form strong interface bonds with a metal.…”