Sub-40-nm half-pitch double patterning with resist freezing process

Hori, Masafumi; Nagai, Takeharu; Nakamura, Atsushi; Abe, Takayoshi; Wakamatsu, Gouji; Kakizawa, Tomohiro; Anno, Yuusuke; Sugiura, Makoto; Kusumoto, Shiro; Yamaguchi, Yoshikazu; Shimokawa, Tsutomu

doi:10.1117/12.772403

Cited by 53 publications

(29 citation statements)

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“…3 Once all simulations are conducted, minimum, nominal and maximum values for each coupling capacitance are recorded and the results are presented in the variational capacitance table.…”

Section: Formentioning

confidence: 99%

“…Notice that intralayer coupling increases on one side, whereas it reduces on the other side. We alter our DOE such that the mask shift parameter S is set equal to -3σ and 3σ con- 3 The DOE can be simplified by eliminating certain corner combinations if they are known not to cause a worst-case corner based on a previous sensitivity analysis. However, the overall simulation time is already not burdensome.…”

Section: Double Patterning Processmentioning

confidence: 99%

See 1 more Smart Citation

ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration

Kahng¹,

Li²,

Peh³

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

549

338

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Double patterning lithography seems to be a prominent choice for 32nm and 22nm technologies. Double patterning lithography techniques require additional masks for a single interconnect layer. Consequently, mask shift-induced overlay errors introduce additional variability into interconnect coupling capacitances. An important open question is whether overlay-induced performance impacts are more significant than performance variations caused by variability in interconnects. We provide TCAD as well as chip-level analyses to determine whether overlay error should receive more attention than interconnect variations during interconnect manufacturing. We develop conclusions to help determine which component should be given more importance in specific double patterning process variants.

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“…3 Once all simulations are conducted, minimum, nominal and maximum values for each coupling capacitance are recorded and the results are presented in the variational capacitance table.…”

Section: Formentioning

confidence: 99%

Section: Double Patterning Processmentioning

confidence: 99%

ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration

Kahng¹,

Li²,

Peh³

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

549

338

View full text Add to dashboard Cite

show abstract

“…Double exposure [1], double patterning [2] [7] and sacrificial spacer double patterning [11] are three major types of double patterning in the International Technology Roadmap for Semiconductors (ITRS) [18], and with variants to enhance printability and reduce variability [3] [12].…”

Section: Introductionmentioning

confidence: 99%

Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures

Coskun

Kahng

Rosing

2009

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools

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Double patterning lithography (DPL) is a likely resolution enhancement technique for IC production in 32nm and below technology nodes. However, DPL gives rise to two independent, uncorrelated distributions of linewidth on a chip, resulting in a 'bimodal' linewidth distribution and an increase in performance variation. [13] suggested that new physical design mechanisms could reduce harmful covariance terms that contribute to this performance variation.In this paper, we propose new bimodal-aware timing analysis and optimization methods to improve timing yield of standardcell based designs that are manufactured using DPL. Our first contribution is a DPL-aware approach to timing modeling, based on detailed analysis of cell layouts. Our second contribution is an ILP-based maximization of 'alternate' mask coloring of instances in timing-critical paths, to minimize harmful covariance and performance variation. Third, we propose a dynamic programming-based detailed placement algorithm that solves mask coloring conflicts and can be used to ensure "double patterning correctness" after placement or even after detailed routing, while minimizing the displacement of timing-critical cells with manageable ECO impact.With a 45nm library and open-source design testcases, our timing-aware recoloring and placement optimizations together achieve up to 232ps (resp. 36.22ns) reduction in worst (resp. total) negative slack, and 78% (resp. 65%) reduction in worst (resp. total) negative slack variation.

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“…Current lithography technology applying for mass production is ArF-immersion (ArF-imm) lithography, however, the resolution is now facing the limit. Thus, to further enhance the resolution, double patterning or self-aligned double patterning techniques using ArF-imm lithography are being applied for 3x nm and 2x nm processes [1][2][3]. Although those processes overcome the resolution limit of ArF-imm lithography, there are concerns relating to the increase in process steps and cost of ownership, and the difficulty of overlay [4].…”

Section: Introductionmentioning

confidence: 99%

Perpendicularly Oriented Cylinders of Si-containing Block Copolymers by Atmospheric Thermal Annealing

Seshimo¹,

Odashima

Maeda

et al. 2016

J. Photopol. Sci. Technol.

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The directed self-assembly (DSA) of block copolymers (BCPs) can realize as one of candidates for next generation lithography. The BCPs for DSA should exhibit a high resolution, an ability to form perpendicularly oriented domains in the thin film by thermal annealing under mild condition, and a high etching selectivity. Here, we report a new Si-containing BCPs targeted to form perpendicularly oriented cylinders in thin films. The hydroxyl groups in the side chains introduced in the Si-containing block provide a good surface free energy (SFE) balance leading to the perpendicular orientation. Furthermore, this orientation can be completed in only one minute atmospheric thermal annealing at 150 °C. Oxygen plasma etching for the thin films results in the achievement of hexagonally packed cylinders.

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Sub-40-nm half-pitch double patterning with resist freezing process

Cited by 53 publications

References 0 publications

ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration

ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration

Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures

Perpendicularly Oriented Cylinders of Si-containing Block Copolymers by Atmospheric Thermal Annealing

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