Sub- $10^{-9}~\Omega $ -cm2 n-Type Contact Resistivity for FinFET Technology

Niimi, Hiroaki; Liu, Zuoguang; Gaidai, Oleg; Mochizuki, Seibu; Fronheiser, Jody; Li, Juntao; Demarest, J.; Zhang, Chen; Liu, Bei; Yang, Jie; Raymond, M.; Haran, Bala; Bu, H.; Yamashita, T.

doi:10.1109/led.2016.2610480

Cited by 55 publications

(23 citation statements)

References 11 publications

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“…This may be induced by a "snowplow effect" in front of the moving amorphous/crystal (a/c) interface during SPR [29]. This characteristic As redistribution can be beneficial for lowering contact resistivity of transistors [30,31].…”

Section: Resultsmentioning

confidence: 99%

Solid Phase Recrystallization in Arsenic Ion-Implanted Silicon-On-Insulator by Microsecond UV Laser Annealing

Tabata

Rozé

Acosta-Alba

et al. 2022

IEEE J. Electron Devices Soc.

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UV laser annealing (UV-LA) enables surfacelocalized high-temperature thermal processing to form abrupt junctions in emerging monolithically stacked devices, where the applicable thermal budget is restricted. In this work, UV-LA is performed to regrow a silicon-oninsulator wafer partially amorphized by arsenic ion implantation as well as to activate the dopants. In a microsecond scale (~10 -6 s to ~10 -5 s) UV-LA process, monocrystalline solid phase recrystallization and dopant activation without junction deepening are evidenced, thus opening various applications in low thermal budget integration flows. However, some concerns remain. First, the surface morphology is degraded after the regrowth, possibly because of the non-perfect uniformity of the used laser beam and/or the formation of defects near the surface involving the excess dopants. Second, many of the dopants are inactive and seem to form deep levels in the Si band gap, suggesting a further optimization of the ion implantation condition to manage the initial crystal damage and the heating profile to better accommodate the dopants into the substitutional sites. Index Terms-laser annealing, solid phase recrystallization, silicon-on-insulator I. INTRODUCTIONowadays, to further explore alternative scaling paths, monolithically stacked devices are emerging [1-8]. However, vertical stacking of multiple functional layers brings severe limitation of the thermal budget applicable to top-tier devices (e.g., 500 °C for 2 h [3,6]), because bottom-tier ones must preserve their functions and performances during subsequent thermal processing steps. One of the most critical challenges is the formation of junctions on the top layers (e.g., source and drain [9] and their extension [8] for metal-oxidesemiconductor field-effect transistors (MOSFET), back-surface

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Section: Resultsmentioning

confidence: 99%

Solid Phase Recrystallization in Arsenic Ion-Implanted Silicon-On-Insulator by Microsecond UV Laser Annealing

Tabata

Rozé

Acosta-Alba

et al. 2022

IEEE J. Electron Devices Soc.

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“…35 This As surface migration may be beneficial for lowering the contact resistivity of transistors. 13,36 The As chemical concentration at 20 nm depth is 1.25 × 10 21 at./cm 3 for Process A, whereas 0.98 × 10 21 at./cm 3 for Process B. Their difference is greater than the measurement error (± 10%).…”

mentioning

confidence: 92%

Microsecond non-melt UV laser annealing for future 3D-stacked CMOS

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Rozé

Thuries

et al. 2022

Appl. Phys. Express

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Three-dimensional (3D) CMOS technology encourages the use of UV laser annealing (UV-LA) because the shallow absorption of UV light into materials and the process timescale typically from nanoseconds (ns) to microseconds (µs) strongly limit the vertical heat diffusion. In this work, µs UV-LA solid phase epitaxial regrowth (SPER) demonstrated an active carrier concentration surpassing 1 × 1021 at./cm3 in an arsenic ion-implanted silicon-on-insulator substrate. After the subsequent ns UV-LA known for improving CMOS interconnect, only a slight (⁓5%) sheet resistance increase was observed. The results open a possibility to integrate UV-LA at different stages of 3D-stacked CMOS.

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“….cm 2 for a doping concentration of 1 × 10 20 |e|/cm 3 and reflects the needs for the injected electrons to cross the interface potential set by the tail states 19 present at the metal-semiconductor interface (Figure 2b). Interestingly, this model leads to contact resistances values relatively close to what has been recently measured experimentally by Hao et al, 15 as illustrated in Figure 3a.…”

Section: Resultsmentioning

confidence: 95%

Study of the Intrinsic Limitations of the Contact Resistance of Metal/Semiconductor Interfaces through Atomistic Simulations

Dabral

Pourtois

Sankaran

et al. 2018

ECS J. Solid State Sci. Technol.

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In this contribution, we report a fundamental study of the factors that set the contact resistivity between metals and highly doped n-type 2D and 3D semiconductors. We investigate the case of n-type doped Si contacted with amorphous TiSi combining firstprinciples calculations with Non-Equilibrium Green functions transport simulations. The evolution of the intrinsic contact resistivity with the doping concentration is found to saturate at ∼2 × 10 −10 .cm 2 for the case of TiSi and imposes an intrinsic limit to the ultimate contact resistance achievable for n-doped Si|amorphous-TiSi (aTiSi). The limit arises from the intrinsic properties of the semiconductors and of the metals such as their electron effective masses and Fermi energies. We illustrate that, in this regime, contacting heavy electron effective mass metals with semiconductor helps reducing the interface intrinsic contact resistivity. This observation seems to hold true regardless of the 3D character of the semiconductor, as illustrated for the case of three 2D semiconducting materials, namely Over the last technology nodes, the continuous reduction of the CMOS dimensions has been pushing the physical limits of the transistor into numerous ends. Consequently, a straightforward linear scaling of device dimensions can no longer cope with all the aspects of the CMOS transistor. For instance, the aggressive scaling of the transistor gate pitch requires that both the gate length and the source/drain (S/D) contact dimensions be reduced in size. This results in the gate, the sidewall spacers and the S/D contacts to compete continuously for space. In addition, the transistor gate length has also to follow a different scaling law and is kept as large as possible to ensure a proper electrostatic control. A direct consequence of this approach is the need to keep on decreasing the S/D contact resistance, which currently constitutes a new bottleneck in the scaling of modern CMOS. Aside from being able to reduce the physical dimensions of the contact, it is paramount to minimize the metal/semiconductor intrinsic resistivity which has now become a major roadblock to be conquered. Recently, the cumulated efforts of the scientific and engineering communities have substantially extended the physical limits of the S/D contact resistance thanks to the increase in the concentration of activated dopants in the semiconductors and to the engineering of their Schottky barrier. The latter is achieved by integrating metals with a weak Fermi level pinning at the interface with the semiconductor. As a result, contact resistivities as low as 2 × 10 Aside from pushing the doping limits in conventional semiconductors, new materials are also being investigated which may allow better scaling and transport by virtue of their properties. Two-dimensional (2D) materials, especially transition metal dichalcogenides, have emerged as possible candidates in this regard 22 for both MOSFET and tunnel based FET applications. 23,24 Electrostatic doping in 2D materials also promises high carrier con...

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Sub- $10^{-9}~\Omega $ -cm2 n-Type Contact Resistivity for FinFET Technology

Cited by 55 publications

References 11 publications

Solid Phase Recrystallization in Arsenic Ion-Implanted Silicon-On-Insulator by Microsecond UV Laser Annealing

Solid Phase Recrystallization in Arsenic Ion-Implanted Silicon-On-Insulator by Microsecond UV Laser Annealing

Microsecond non-melt UV laser annealing for future 3D-stacked CMOS

Study of the Intrinsic Limitations of the Contact Resistance of Metal/Semiconductor Interfaces through Atomistic Simulations

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