Sub 0.1 μm nMOSFETs fabricated using experimental design techniques to optimise performance and minimise process sensitivity

Kubicek, Stefan; Biesemans, S.; Wang, Q.F.; Maex, Karen; Meyer, K. De

doi:10.1109/vlsit.1995.520879

Cited by 5 publications

(1 citation statement)

References 2 publications

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“…For a given process condition, regular try-and-error method cannot guarantee to achieve optimized implant conditions even with many cycle times and many wafers. DOE is a powerful method to deal with multiple response optimizations in a multi-dimensional space [1][2]. However, the number of experimental runs using classical response-surface-modeling (RSM) DOE can easily exceed 25 when number of input variables reach 4 or above, which makes it not practical for semiconductor manufacturing since one lot contains only 25 wafers.…”

Section: Introductionmentioning

confidence: 99%

A Method of Optimizing Mosfets through Engineering Knowledge-Based Analysis and Efficient Design of Experiments for 28nm Technology Node and Beyond

Shi

Yang

et al. 2014

ECS Trans.

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In this paper, a practice of design of experiments and data analysis for 28nm technology NMOS devices was introduced. Optimal design with I-optimality criterion was used for 5 input variables with 3 levels for each device, where total 23 runs/wafers were generated. Based on the response surface models by an excellent regression on device parametric data, both automatic maximum desirability analyses by JMP software and engineering knowledgebased analysis were carried out. The two methods generated similar prediction and the latter one helps gaining more insight on the device optimization. The prediction was exactly reproduced in silicon experiment.

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Section: Introductionmentioning

confidence: 99%