Sturdy MASH - modulator

Maghari, Nima; Kwon, Sunwoo; Temes, Gábor C.; Moon, Un-Ku

doi:10.1049/el:20062718

Cited by 66 publications

(34 citation statements)

References 2 publications

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“…There are several previous works reported on the structure of Sturdy MASH (SMASH) [1], [2] without silicon data and on MASH structure with silicon data in 0.18µm CMOS process [3]. For simplicity, we have chosen 2-2 MASH structure to implement a 4 th order Σ-∆ ADC.…”

Section: Mash Structurementioning

confidence: 99%

A 65nm 1.2V 16-bit audio codec sigma-delta ADC in 2-2 MASH architecture with temperature-compensated biasing

Choi

Lam

2011

2011 IEEE International Conference of Electron Devices and Solid-State Circuits

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A 16-bit audio codec sigma-delta (Σ Σ Σ Σ-∆ ∆ ∆ ∆) ADC including a decimation filter, implemented in a 65nm process, is reported measured results. The ADC operates with a 1.2V supply voltage and a 256 times over-sampling, achieving a Spurious-free Dynamic Range (SFDR) of 70dB. The 2-2 MASH architecture has been employed to reduce the required capacitor ratio for improved matching. A temperature compensation scheme is also included in the biasing circuit to limit the power consumption at high temperatures.

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Section: Mash Structurementioning

confidence: 99%

A 65nm 1.2V 16-bit audio codec sigma-delta ADC in 2-2 MASH architecture with temperature-compensated biasing

Choi

Lam

2011

2011 IEEE International Conference of Electron Devices and Solid-State Circuits

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“…Hence, highly accurate analog building blocks are needed to minimize this undesired effect, leading to higher power dissipation. Fig.2 shows a general form of the SMASH structure presented in [2]. The main advantage of SMASH is that it uses only analog filters, so digital filters are removed and analog circuit building blocks are relaxed.…”

Section: Mash Versus Smashmentioning

confidence: 99%

“…The ove where (2) Satisfying above equation will result in fourth order noise shaping for both E 1 and E 2 , with all zeros placed at DC. As discussed in detail in [3], this structure is less susceptible to opamp DC gain compared to the traditional MASH structure.…”

Section: Efficient Smash Structuresmentioning

confidence: 99%

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Multi-loop efficient sturdy MASH delta-sigma modulators

Maghari

Moon

2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-An extended version of sturdy MASH delta-sigma modulators is presented in this paper. Improved performance is achieved using in-band zero optimization. The challenges towards high order multi-loop modulators are discussed and a new multi-loop modulator is presented. This modulator benefits from a MASH architecture in the final loop to preserve stability, while the main loop benefits from relaxed circuit building blocks of the SMASH structure. Extensive simulation results are provided to prove the efficiency of this structure.

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“…However MSCL ΣΔ modulators give a signal to noise ratio (SNR) weaker than that obtained by traditional MASH structures. To improve the modulator performance, structures called SMASH and MOSMASH were proposed in 2006 and 2007 [4][5]. These two structures use the non-unity STF second order modulators in cascade with a global feedback.…”

Section: Introductionmentioning

confidence: 99%

Generalized multi-stage closed loop sigma delta modulator

Nguyen

Fakhoury

Loumeau

et al. 2011

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

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This paper presents a new high order cascade sigma delta modulator called GMSCL. It uses first and/or second order modulator with unity signal transfer function in each stage and a global feedback to lower the sensitivity to circuit imperfections, to relax the output swing and gain requirements of amplifiers and to avoid digital prefiltering in the quantization error cancellation logic. The zeros of the noise transfer function are optimized to improve the modulator performance. This topology is thus very suitable for wideband low voltage applications. Behavioral simulations demonstrate the high efficiency of the proposed topology comparing to existing cascade topologies. I. INTRODUCTIONWideband sigma delta (ΣΔ) modulators with unity signal transfer function (STF) are good candidates for low oversampling rate, low-voltage implementation and high resolution ADC [1-2]. By making the STF unity, the integrators ideally process quantization error only, thus relaxing the requirements of amplifier gain, nonlinearity and output swing.Because of low oversampling rate in wideband applications, multistage noise shaping (MASH) architectures are usually employed to achieve the required performance. These topologies do not suffer from the stability problem of high-order loops, but are sensitive to mismatch between the analogue and digital prefiltering [3].To lower the sensitivity to circuit imperfections, the multistage closed-loop (MSCL) ΣΔ modulator was proposed in 1995 [1]. The MSCL modulator uses unity STF first order and monobit ΣΔ modulators in each stage and a global feedback is introduced from the output to each input. The STF of the MSCL modulator still stays unity and thanks to the global feedback non prefilering is needed in the quantization error logic contrary to MASH topologies . However MSCL ΣΔ modulators give a signal to noise ratio (SNR) weaker than that obtained by traditional MASH structures. To improve the modulator performance, structures called SMASH and MOSMASH were proposed in 2006 and 2007 [4-5]. These two structures use the non-unity STF second order modulators in cascade with a global feedback. Nevertheless, they are sensitive to circuit imperfections. Recently a MSCL modulator using unity STF second order ΣΔ modulators was presented [6]. Because of the use of unity STF modulators, this modulator is better than SMASH modulator in terms of output swing and of tolerance to nonlinearities of amplifiers [6].This paper proposes a new high order ΣΔ modulator called GMSCL (Generalized Multi-Stage Closed Loop Sigma Delta

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Sturdy MASH - modulator

Cited by 66 publications

References 2 publications

A 65nm 1.2V 16-bit audio codec sigma-delta ADC in 2-2 MASH architecture with temperature-compensated biasing

A 65nm 1.2V 16-bit audio codec sigma-delta ADC in 2-2 MASH architecture with temperature-compensated biasing

Multi-loop efficient sturdy MASH delta-sigma modulators

Generalized multi-stage closed loop sigma delta modulator

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