Study on TSV isolation liners for a Via Last approach with the use in 3D-WLP for MEMS

Abstract

This paper discusses approaches for the isolation of deep high aspect ratio through silicon vias (TSV) with respect to a Via Last approach for micro-electro-mechanical systems (MEMS). Selected TSV samples have depths in the range of 170…270 µm and a diameter of 50 µm. The investigations comprise the deposition of different layer stacks by means of subatmospheric and plasma enhanced chemical vapour deposition (PECVD) of tetraethyl orthosilicate; Si(OC2H5)4 (TEOS). Moreover, an etch-back approach and the selective deposition on SiN were also included in the investigations. With respect to the Via Last approach, the contact opening at the TSV bottom by means of a specific spacer-etching method have been addressed within this paper. Step coverage values of up to 74 % were achieved for the best of those approaches. As an alternative to the SiO2-isolation liners a polymer coating based on the CVD of Parylene F was investigated, which yields even higher step coverage in the range of 80 % at the lower TSV sidewall for a surface film thickness of about 1000 nm. Leakage current measurements were performed and values below 0.1 nA/cm2 at 10 kV/cm were determined for the ParyleneF films which represents a promising result for the aspired application to Via Last MEMS-TSV

Wafer Scale Insulation of High Aspect Ratio Through-Silicon Vias by iCVD

“…11,12 Previous works have combined PECVD with SACVD, but the obtained films still exhibit insufficient electrical characteristics. 13,14 Besides, atomic layer deposition (ALD) has been investigated as an alternative method for the deposition of an insulating layer for TSVs. However, although the conformality of the deposition is very good, the low deposition rate makes the ALD process not cost-effective.…”

Review—The Mediating Effect of Chemically Oxidized Silicon Surface on the P4VP Electrografting for Silicon Electrical Insulation

“…1,3 During the last decade, Si insulation using polymer films was developed as an alternative to traditional SiO 2 . Among them, the chemical vapor deposition of parylene (poly(p-xylylene)) films 3-6 and the electrografting of poly-4-vinylpyridine (P4VP) in aqueous media have shown promising results.7-9 Indeed, they can be deposited at room temperature or up to 300• C. 3,10 Parylene HT films have been demonstrated to be stable up to a temperature of 350• C 11 , to avoid the appearance of cracks and adhesion loss in the dielectric film. 5,12 Electrografted P4VP were shown to withstand temperatures up to 450…”

“…Nevertheless, the deposition of a good conformal SiO 2 film to insulate high aspect ratio TSV is hardly achievable and is costly due to the required growth condition of CVD methods. 1,3 During the last decade, Si insulation using polymer films was developed as an alternative to traditional SiO 2 . Among them, the chemical vapor deposition of parylene (poly(p-xylylene)) films [3][4][5][6] and the electrografting of poly-4-vinylpyridine (P4VP) in aqueous media have shown promising results.…”

“…1,3 During the last decade, Si insulation using polymer films was developed as an alternative to traditional SiO 2 . Among them, the chemical vapor deposition of parylene (poly(p-xylylene)) films [3][4][5][6] and the electrografting of poly-4-vinylpyridine (P4VP) in aqueous media have shown promising results. [7][8][9] Indeed, they can be deposited at room temperature or up to 300 • C. 3,10 Parylene HT films have been demonstrated to be stable up to a temperature of 350 • C 11 , to avoid the appearance of cracks and adhesion loss in the dielectric film.…”

“…Among them, the chemical vapor deposition of parylene (poly(p-xylylene)) films [3][4][5][6] and the electrografting of poly-4-vinylpyridine (P4VP) in aqueous media have shown promising results. [7][8][9] Indeed, they can be deposited at room temperature or up to 300 • C. 3,10 Parylene HT films have been demonstrated to be stable up to a temperature of 350 • C 11 , to avoid the appearance of cracks and adhesion loss in the dielectric film. 5,12 Electrografted P4VP were shown to withstand temperatures up to 450 • C, 8 making this process a more versatile alternative to SiO 2 and parylene for silicon insulation in microelectronic systems.…”