Wafer Scale Insulation of High Aspect Ratio Through-Silicon Vias by iCVD

Abstract

In microelectronics, one of the main 3D integration strategies consists of vertically stacking and electrically connecting various functional chips using through-silicon vias (TSVs). For the fabrication of the TSVs, one of the challenges is to conformally deposit a low dielectric constant insulator thin film at the surface of the silicon. To date, there is no universal technique that can address all types of TSV integration schemes, especially in the case requiring a low deposition temperature. In this work, an organosilicate polymer deposited by initiated chemical vapor deposition (iCVD) was developed and integrated as an insulating layer for TSVs. Process studies have shown that poly(1,3,5-trivinyl-1,3,5-trimethyl cyclotrisiloxane) (P(V 3 D 3 )) can present good conformality on high aspect ratio features by increasing the substrate temperature up to 100 °C. The trade-off is a moderate deposition rate. The thermal stability of the polymer has been investigated, and we show that a thermal annealing at 400 °C (with or without ultraviolet exposure) allows the stabilization of the dielectric films by removing residual oligomers. Then, P(V 3 D 3 ) was integrated in high aspect ratio TSV (10 × 100 μm) on 300 mm silicon wafers using a standard integration flow for TSV metallization. Functional devices were successfully fabricated (including daisy chains of 754 TSVs) and electrically characterized. Our work shows that the metallization barrier should be carefully selected to eliminate the appearance of voids at the top corner of the TSV after the Cu annealing step. Moreover, an appropriate integration process should be used to avoid the appearance of cohesive cracks in the liner. This work constitutes a first proof of concept of the use of an iCVD polymer in a quasi-industrial microelectronic environment. It also highlights the benefit of iCVD as a promising technique to deposit conformal dielectric thin films in a microelectronic pilot line environment.