Study on the poly bump defect by TEM failure analysis

Soo, Chi Wen; Liu, B.; Er, E.; Zhao, S. P.; Lam, Jeffrey; Liu, W.; Mun, Jihun

doi:10.1109/ipfa.2015.7224383

Cited by 2 publications

(2 citation statements)

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“…As a result, the spherical bump defects are formed. For 3D NAND, as the number of stacked layers increases, the small bump will be enlarged seriously, which may affect subsequent processes and even device functions [4]. Therefore, it is very important to solve the defects to improve the yield of 3D NAND flash memory.…”

Section: Introductionmentioning

confidence: 99%

Optimization of Bump Defect at High-Concentration In-Situ Phosphorus Doped Polysilicon/TEOS Oxide Interface for 3D NAND Flash Memory Application

Zhao

Xia

Wu³

et al. 2021

IEEE J. Electron Devices Soc.

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In the 3D NAND Flash memory manufacturing process, high-concentration in-situ phosphorus-doped polysilicon and TEOS oxide stack will produce bump defects at the interfaces, causing pattern defects and electrical failures. The formation mechanism of bump defects caused by oxygen-containing groups and phosphorus at the lower and upper interfaces of phosphorus-doped polysilicon is investigated in detail. Two methods were demonstrated to reduce bump defects, wet processing and Rapid Thermal Oxidation (RTO). The wet processing is to remove oxygen-containing groups and phosphorus, while the RTO process increases the solubility of phosphorus in silicon. Both methods have significantly reduced bump defects and greatly increased the yield rate, and further verify the proposed formation mechanism of bump defects.Index Terms-bump defects, phosphorus-doped polysilicon, TEOS, wet processing, RTO.

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Section: Introductionmentioning

confidence: 99%

Optimization of Bump Defect at High-Concentration In-Situ Phosphorus Doped Polysilicon/TEOS Oxide Interface for 3D NAND Flash Memory Application

Zhao

Xia

Wu³

et al. 2021

IEEE J. Electron Devices Soc.

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“…It is a form of electron microscope which derives an image from electrons that have passed through the device. The image is formed at once rather than by scanning [35][36][37][38]. TEM uses microscopy technique in which a beam of electrons is transmitted through a very thin electrical device, interacting with the device as it passes through it and generates a projection image.…”

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confidence: 99%

Efficient Fault Localization and Failure Analysis Techniques for Improving IC Yield

Oberai

Yuan

2018

Electronics

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With the increase in the complexity of the semiconductor device processes and increase in the challenge to satisfy high market demands, enhancement in yield has become a crucial factor. Discovering and reacting to yield problems emerging at the end of the production line may cause unbearable yield loss leading to larger times to market. Thus, time and cost involved in fault isolation may be significantly shortened by effectively utilizing the fault diagnosis technology and supporting yield improvements. Hence for yield analysis, a highly integrated data network with software analysis tools have been established to reduce the fault analysis time. Synopsys Avalon, a product used for fault localization is described in this paper which aids in achieving better integrated circuit yields. This paper also illustrates various fault localization techniques for faster problem identification and discusses a few analytical tools like photon emission microscope and transmission emission microscope for faster determination of device failures.

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Study on the poly bump defect by TEM failure analysis

Cited by 2 publications

References 0 publications

Optimization of Bump Defect at High-Concentration In-Situ Phosphorus Doped Polysilicon/TEOS Oxide Interface for 3D NAND Flash Memory Application

Optimization of Bump Defect at High-Concentration In-Situ Phosphorus Doped Polysilicon/TEOS Oxide Interface for 3D NAND Flash Memory Application

Efficient Fault Localization and Failure Analysis Techniques for Improving IC Yield

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