Study of the interfacial properties of amorphous silicon/n‐type crystalline silicon heterojunction through static planar conductance measurements

Abstract

We have previously shown from static planar conductance measurements that a strong inversion layer does exist in c‐Si at the (n) a‐Si:H/ (p) c‐Si interface. This allowed us to determine the conduction band offset with a good precision (ΔEC = 0.15 +/– 0.04 eV). The same technique is now applied to study (p) a‐Si:H/ (n) c‐Si interfaces. We demonstrate that a strong inversion layer (of holes) also exists at the c‐Si surface of this hetero‐interface. Analysis of our planar conductance data with the help of numerical simulations allows us to set a lower limit to the valence band offset, ΔEV = EV,a‐Si:H − EV, c‐Si: ΔEV > 0.28 eV. (© 2010 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Analysis of lateral transport through the inversion layer in amorphous silicon/crystalline silicon heterojunction solar cells

“…Increasing DE vb at the a-Si:H/ c-Si interface increases the hole concentration at the surface of the c-Si, as can be seen in the inset of Figure 5. Favre et al 13 simulated the same structure without the intrinsic layer, which changes the band bending, but at room temperature our values of the surface hole concentration, obtained by evaluating the integral in Eq. (2) without illumination, have the same DE vb trend.…”

“…Recently, there has been experimental confirmation of the existence of the inversion layer using capacitive methods, 9,10 planar conductivity measurements, [11][12][13] and conductive probe atomic force microscopy. 14,15 Until now, the inversion layer has been considered only as a tool to characterize the band offsets at the a-Si:H/c-Si interface 16,17 and its influence on lateral transport in operating devices has not yet been analyzed.…”

Influence of the amorphous/crystalline silicon heterostructure properties on planar conductance measurements

“…The method is based on the existence of a strongly inverted layer in the crystalline material at the interface if a highly doped (n) a-Si:H layer is deposited on a (p) c-Si substrate [5,6], or for the inverted structure [7]. This forms a conductive channel that strongly depends on the band bending and thus on the band offsets.…”

Interface properties of amorphous-crystalline silicon heterojunctions prepared using DC saddle-field PECVD

“…The surface conductances for the films grown on crystalline silicon substrates correspond to increasing i-layer thickness (0, 4, and 10 min of deposition at a nominal deposition rate of 1 nm/min). As expected from studies on RF PECVD a-Si:H films [10][11][12], the samples on crystalline silicon have a much higher conductance and a weaker temperature dependence, i.e. a lower activation energy (see Table 2), which suggests the presence of a strong inverted layer at the interface.…”