Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor

Touloupis, Emmanuel; Flint, James A.; Chouliaras, V.A.; Ward, David

doi:10.1109/tc.2007.70766

Cited by 45 publications

(24 citation statements)

References 42 publications

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“…Touloupis et al [10] used RTL-simulation-based fault injection techniques to study the effect of faults in registers. The required design effort and computational cost of RTL-based fault injection, however, limits its applicability.…”

Section: Related Workmentioning

confidence: 99%

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Jiang

Liu

Meyer

2014

Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI

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Recent studies have shown a dramatic increase in multi-bit upset (MBU) events and related errors as transistors continue to shrink. To assist designers with addressing MBU in microprocessor register files, we have extended an architectural description language, ADL, to simulate and analyze the effect of MBU on the fault coverage of hardware mitigation techniques. Our approach (a) considers the effect of SRAM layout on MBU patterns, (b) considers the datadependent nature of transient upsets, and (c) runs benchmarks to completion to accurately evaluate coverage. To accelerate fault injection campaigns, we propose a suite of techniques that reduce the execution time of individual trials without compromising accuracy by only simulating mitigation techniques when faults are present and stopping simulation entirely when all errors have been detected or corrected. When evaluating parity, SECDED, and 2-bit 2D ECC, we achieve a mean fault injection performance speedup of 5.1×, but up to nearly 60× in one case.

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Section: Related Workmentioning

confidence: 99%

Mb-Fica

Jiang

Liu

Meyer

2014

Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI

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“…The latter study triggered the definition of a new probabilistic framework for incorporating vulnerability of memories to different fault multiplicities into AVF [12]. Finally, [8] investigates the effects of multiple non-concurrent faults on the operation of a microprocessor. Both [12] and [13] conclude that the probability of non-clustered double faults is negligible, and can be eliminated with simple scrubbing techniques [13].…”

Section: Related Workmentioning

confidence: 99%

“…1. Frequency distribution of number of faulty bits generated per SEU for different process sizes [4] by reduced power supply voltage, increased clock frequency, crosstalk and electromigration effects [8].…”

Section: Introductionmentioning

confidence: 99%

“…A large area percentage of such circuits is occupied by several in-core memory arrays, typically implemented using SRAM cells. To the best our knowledge, while extensive studies have been performed on increasing the reliability of caches and register files [9], [10], there are only a few MBU studies targeting modern microprocessor modules [11], [8], [12], [13]. The reason for the absence of such studies is three-fold: In this paper, we address the aforementioned issues and we present a multiple bit error vulnerability analysis study in a complex modern microprocessor module.…”

Section: Introductionmentioning

confidence: 99%

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Investigating the limits of AVF analysis in the presence of multiple bit errors

Maniatakos

Michael

Makris

2013

2013 IEEE 19th International on-Line Testing Symposium (IOLTS)

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We investigate the complexity and utility of performing Multiple Bit Upset (MBU) vulnerability analysis in modern microprocessors. While the Single Bit Flip (SBF) model constitutes the prevailing mechanism for capturing the effect of Single Event Upsets (SEUs) due to alpha particle or neutron strikes in semiconductors, recent radiation studies in 90nm and 65nm technology nodes demonstrate that up to 55% of such strikes result in Multiple Bit Upsets (MBUs). Consequently, the accuracy of popular vulnerability analysis methods, such as the Architecural Vulnerability Factor (AVF) and Failures In Time (FIT) rate estimates based on the SBF assumption comes into question, especially in modern microprocessors which contain a significant amount of memory elements. Towards alleviating this concern, we present an extensive infrastructure which enables MBU vulnerability analysis in modern microprocessors. Using this infrastructure and a modern microprocessor model, we perform a large scale MBU vulnerability analysis study and we report two key findings: (i) the SBF fault model overestimates vulnerability by up to 71%, as compared to a more realistic modeling and distribution of faults in the 90nm and 65nm processes, and (ii) the rank-ordered lists of critical bits, as computed through the SBF and MBU models, respectively, are very similar, as indicated by the average rank difference of a bit which is less than 1.45%.

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“…Prior work [10], [11], [12], [13] has studied the impact of double bit-flip errors on a program, i.e., injecting two errors in a single word or multiple words. These papers assume (without providing evidence) that single/double bit-flip errors are sufficient when measuring programs' error resilience.…”

Section: Introductionmentioning

confidence: 99%

One Bit is (Not) Enough: An Empirical Study of the Impact of Single and Multiple Bit-Flip Errors

Sangchoolie¹,

Pattabiraman

Karlsson

2017

2017 47th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)

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Abstract-Recent studies have shown that technology and voltage scaling are expected to increase the likelihood that particle-induced soft errors manifest as multiple-bit errors. This raises concerns about the validity of using single bit-flips for assessing the impact of soft errors in fault injection experiments. The goal of this paper is to investigate whether multiple-bit errors could cause a higher percentage of silent data corruptions (SDCs) compared to single-bit errors. Based on 2700 fault injection campaigns with 15 benchmark programs, featuring a total of 27 million experiments, our results show that single-bit errors in most cases yields a higher percentage of SDCs compared to multiple-bit errors. However, in 8% of the campaigns we observed a higher percentage of SDCs for multiple-bit errors. For most of these campaigns, the highest percentage of SDCs was obtained by flipping at most 3 bits. Moreover, we propose three ways of pruning the error space based on the results.

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Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor

Cited by 45 publications

References 42 publications

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Investigating the limits of AVF analysis in the presence of multiple bit errors

One Bit is (Not) Enough: An Empirical Study of the Impact of Single and Multiple Bit-Flip Errors

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