Study of Selective Dry Etching Effects of 15-Cycle Si0.7Ge0.3/Si Multilayer Structure in Gate-All-Around Transistor Process

Liu, Enxu; Li, Junjie; Zhou, Na; Rui, Chen; Shao, Hua; Gao, Jianfeng; Zhang, Qingzhu; Kong, Zhenzhen; Lin, Hongxiao; Zhang, Chenchen; Lai, Pan-Pan; Chao, Yang; Liu, Yang; Wang, Guilei; Zhao, Chao; Yang, Tao; Li, Junfeng; Luo, Jun; Wang, Wenwu

doi:10.3390/nano13142127

Cited by 3 publications

(1 citation statement)

References 27 publications

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“…From the figure, it can be observed that the inner spacer cavities exhibit a rectangular profile, and there is no noticeable damage to the nanosheets at both ends. The inner spacer cavities exhibit uniform depth without significant microloading effects or etching depth non-uniformity, 22 providing a prerequisite for fabricating uniformly thick inner spacers. Additionally, from the Fig.…”

Section: Resultsmentioning

confidence: 99%

Study of Inner Spacer Module Process for Gate All Around Field Effect Transsistors

Yang,

Li,

Liu

et al. 2024

ECS J. Solid State Sci. Technol.

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Gate-All-Around(GAA) transistor is the most competitive device for the replacement of Fin Field-Effect Transistor (FinFET). Integrating the inner spacer module into process flow of manufacturing GAA devices still faces significant challenges.In this study, dummy gates were included and the most critical processes for inner spacer, such as cavity etching, dielectric material conformal filling and precise etching back process were studied.The inner spacer cavity with a depth of 10.10 nm was achieved using isotropic etching, and dielectric filling was completed by low pressure chemical deposition (LPCVD).Finally, an inner spacer with 9.35 nm thickness is formed after precise etching the dielectric material. Furthermore，to verify the physical isolation of the inner spacer, a selective epitaxy was developed on the Source/Drain region, achieving better process results. This research will provide important references for the industry to manufacture GAA devices, especially inner spacers.

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Section: Resultsmentioning

confidence: 99%

Study of Inner Spacer Module Process for Gate All Around Field Effect Transsistors

Yang,

Li,

Liu

et al. 2024

ECS J. Solid State Sci. Technol.

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Study of selective dry etching Si0.7Ge0.3 with different plasma source in process of gate-all-around FET

Liu,

Yang,

et al. 2024

Advanced Etch Technology and Process Integration for Nanopatterning XIII

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The lateral gate-all-around (GAA) field effect transistor is considered to be the most promising candidate for the next generation of logic devices at the 3nm technology node and beyond. SiGe plays an important role as a sacrificial layer in the GAA device, which requires isotropic etching, and the quality of the etching has a critical impact on the device performance. However, there is no definite scheme in the industry for the choice of etching method. In this paper, we choose two etching methods-ICP(Inductively coupled Plasma) and RPS (Remote Plasma Source) etching according to the presence or absence of particle incidence. The profile and etching effect of the two etching methods are analyzed by PEGASUS simulation software. The presence or absence of particle incidence has different effects on the damage of the structure, the inconsistency of etching amount and the reflection of the particles on the Si surface. Compared with ICP etching, the optimization of RPS etching on etching damage and etch amount consistency is verified by TEM and roughness characterization . And through the extraction of MOSCAP capacitance, it is found that the density of interface states(Dit) after ICP etching is 3.5 times higher than that of RPS etching.

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Study of precisely controlled selective isotropic quasi-ALE of SiGe

Lai,

Li,

Shao

et al. 2024

Advanced Etch Technology and Process Integration for Nanopatterning XIII

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In gate-all-around nanosheet (GAA-NS) transistor manufacturing, the SiGe layer plays an important role as a sacrificial layer, requiring precisely controlled and highly selective isotropic etching. In our previous work, we proposed a novel isotropic selective quasi-atomic layer etching (quasi-ALE) method based on O 2 plasma self-limiting oxidation and CF 4 /C 4 F 8 self-limiting selective etching. A vertical nanowire transistor with a diameter less than 20 nm and an accuracy error less than 0.3nm has been developed. In this paper, we adopt this method to cavity etching of horizontally stacked nanosheets, using an ICP source to perform self-limiting oxidation of the SiGe layer followed by self-limiting selective removal of oxide (a two-step self-limiting cycle) to form inner spacer cavity. Experimental results show that compared with the strong dependence of the etching amount on SiGe thickness and Ge composition in traditional ICP dry etching, the quasi-ALE technology tends to weaken this size and concentration loading effect due to the self-limiting of each cycle reaction. In addition, we also demonstrated the latest progress in corresponding ALE simulation using a commercial feature-scale plasma process simulator named PEGASUS. The simulation results show that the SiGe etching amount per cycle (EPC) is about 0.3nm, which is basically consistent with the experimental results. This quasi-ALE method demonstrates promising performance for preparing GAA device channels, nanosensors, and other application in future.

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Study of Selective Dry Etching Effects of 15-Cycle Si0.7Ge0.3/Si Multilayer Structure in Gate-All-Around Transistor Process

Cited by 3 publications

References 27 publications

Study of Inner Spacer Module Process for Gate All Around Field Effect Transsistors

Study of Inner Spacer Module Process for Gate All Around Field Effect Transsistors

Study of selective dry etching Si0.7Ge0.3 with different plasma source in process of gate-all-around FET

Study of precisely controlled selective isotropic quasi-ALE of SiGe

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