2017
DOI: 10.1016/j.spmi.2016.11.053
|View full text |Cite
|
Sign up to set email alerts
|

Study of G-S/D underlap for enhanced analog performance and RF/circuit analysis of UTB InAs-OI-Si MOSFET using NQS small signal model

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1

Citation Types

0
2
0

Year Published

2019
2019
2022
2022

Publication Types

Select...
6

Relationship

1
5

Authors

Journals

citations
Cited by 8 publications
(2 citation statements)
references
References 31 publications
0
2
0
Order By: Relevance
“…In [34,35], we know that the lifetime of the non-equilibrium carrier can be calculated by the experiment of measuring the change of the concentration of the non-equilibrium carrier. According to the Heisenberg uncertainty principle [36], when the product of its lifetime and energy needs to be greater than the Heisenberg constant, a non-equilibrium carrier to have an effect in a semiconductor, as follows:…”
Section: The Limit Small Voltage Signal Theorymentioning
confidence: 99%
“…In [34,35], we know that the lifetime of the non-equilibrium carrier can be calculated by the experiment of measuring the change of the concentration of the non-equilibrium carrier. According to the Heisenberg uncertainty principle [36], when the product of its lifetime and energy needs to be greater than the Heisenberg constant, a non-equilibrium carrier to have an effect in a semiconductor, as follows:…”
Section: The Limit Small Voltage Signal Theorymentioning
confidence: 99%
“…In [11], the effect of channel scaling on drain current and transconductance of III-V quantum well FET is reported. The effect of gate underlap on the device and circuit performance is reported in [12]. The effect of buried oxide scaling on the device and circuit performance is reported in [13].…”
Section: Introductionmentioning
confidence: 99%