Analysis of scaling of thickness of the buffer layer on analog/RF and circuit performance of InAs‐OI‐Si MOSFET using NQS model

Abstract

With use of III‐V material in the channel region of a metal‐oxide‐semiconductor (MOS) transistor, interface buffer layers above and below the channel region are necessary to reduce several sources of scattering of the inversion charge carriers. This work presents a detailed analysis of effect of scaling down thickness of the top buffer layer of a buffered InAs‐OI‐Si metal‐oxide‐semiconductor field effect transistor (MOSFET) on electrostatic integrity, carrier mobility, analog/RF, linearity, and circuit performance using well‐calibrated 2D technology computer‐aided design simulation. We further develop non–quasi‐static small‐signal equivalent circuit model of the device. The model results have been compared with experimental results and good accuracy of our model is demonstrated. Both the model and numerical simulation results have been used in our study. In‐depth analysis of behaviour of several performance parameters at DC and radio frequency (RF) is presented with analytical explanations and numerical simulation results. A common source amplifier is designed and simulated in SPICE framework using the equivalent circuit model. From the study, we find that the quantum well that is formed in the buffer/channel/buffer layers needs to be formed as near to the oxide/semiconductor interface as possible for optimum performance.