Performance Assessment of CMOS circuits using III-V on Insulator MOS Transistors

Improvement in the Performance of III-V Channel Based Ultra-Thin Junction-Less-Hybrid CMOS Circuits with Mixed Mode Analysis

“…Furthermore, the intrinsic gain g m /g d is mostly influenced by g d , and as g d increases, gain decreases in GaAs FETs. 22 As a consequence, as shown in Fig. 8, the voltage gain (dV out /dV in ) of the hybrid CMOS inverter is lower than that of the Si-based CMOS inverter.…”

“…6a and 6b reveal the enhanced drain current due to the higher value of electron and hole mobility and saturation velocity of GaAs and Ge compared to Si. 22,27,30 The back gate voltage, V gb is set to −1 and 1 V for the simulation of transfer characteristics of both P-and N-MOS. The trans-conductance (g m ) vs gate voltage of both p and n-channel MOS transistors is revealed in Fig.…”

“…In GaAs transistors, a higher g d value results in a lower intrinsic gain (g m /g d ) as compared to Si transistors. 22 Figure 8 depicts the voltage transfer characteristic (VTC) and voltage gain graphs for a hybrid CMOS inverter composed of a GaAs n-JL-DG-MOSFET and a Ge p-JL-DG-MOSFET with an equivalent Si CMOS inverter. In this simulation, the width ratio of p-and n-MOSFETs is fixed to 2:1.…”

“…When both p-and n-MOSFETs are at the saturation region, the highest voltage gain is obtained. 22 The sharpness of the VTC or gain graph is proportionate to the sum of the trans-conductance (g m ) of the p-and n-MOSFETs and inversely proportional to the total output conductance of aforesaid devices. 28 Because of the increased carrier mobility in both devices, the sum of the trans-conductance for the hybrid inverter is greater.…”

“…6a, which is governed by high hole mobility and saturation velocity. 22 Similarly, the fall time is mostly caused by the discharge of the load capacitor, which is handled by the device's N-MOS. When compared to Si N-MOS, GaAs N-MOS has a shorter rise time due to its higher driving current, as seen in Fig.…”