Study of Analog/Rf and Stability Investigation of Surrounded Gate Junctionless Graded Channel MOSFET(SJLGC MOSFET)

Abstract

This paper explores the potential advantage of surrounded gate junctionless graded channel (SJLGC) MOSFET in the view of its Analog, RF performances using ATLAS TCAD device simulator. The impact of graded channel in the lateral direction on the potential, electric field, and velocity of carriers, energy band along the channel is investigated systematically. The present work mainly emphasises on the superior performance of SJLGC MOSFET by showing higher drain current (ID) , transconductance (gm) ,cut off frequency (fT) , maximum frequency of oscillation (fmax) , critical frequency (fK) .The drain current is improved by 10.03 % in SJLGC MOSFET due to the impact of grading the channel. There is an improvement in fT, fmax, fK by 45%, 29% and 18% respectively in SJLGC MOSFET showing better RF Performance. The dominance of the SJLGC MOSFET over SJL MOSFET is further elucidated by showing 74% improvement in intrinsic voltage gain (gm / gds) indicating its better applications in sub threshold region. But the transconductance generation factor of SJLGC MOSFET is less than SJL MOSFET in the subthreshold region. The intrinsic gate delay (ζD) of SJLGC MOSFET is less in comparison to SJL MOSFET due to the impact of lower gate to gate capacitance (CGG) suggesting better digital switching applications. The simulation results reveal that SJLGC MOSFET can be a competitive contender for the coming generation of RF circuits covering a broad range of operating frequencies in RF spectrum.

The Investigation of graded channel effect on Analog/Linearity Parameter Analysis of junctionless surrounded gate graded channel MOSFET

“…The charge carriers of both the devices face different electric field due to which there is a faster increase in centre potential of GAA-JLGC than the traditional one [48]. A discontinuous electric field is marked in JLGC MOSFET having two peaks [48] . But junctionless surrounded gate MOSFET is having one electric field peak .…”

“…10. In graded channel architecture there is a increase in carrier transportation towards the drain end due to reduced electric field [48]. Although both of the devices have surrounded gate structure but the impact of gate controllability in JLSGGC MOSFET is more in focusing the electrons in the channel towards the drain end owing to their higher transportation efficiency .…”