Investigation of graded channel effect on analog/linearity parameter analysis of junctionless surrounded gate graded channel MOSFET

Abstract

Linearity analysis of nanoscale devices is a vital issue as nonlinearity behavior is exhibited by them when employed in circuits for microwave and RF applications. In this work, a junctionless surrounded gate-graded channel MOSFET (JLSGGC MOSFET) is investigated thoroughly to analyze its linearity performance with the help of ATLAS tool of technology computer-aided design. The proposed device is compared systematically with the conventional junstionless surrounded gate MOSFET(JLSG MOSFET) to investigate their linearity. To evaluate the linearity, the figure of merits such as higher-order transconductance (Gm1, Gm2), intercept points(VIP2, VIP3, IIP3), IMD3 and 1 dB—compression point(P1 dB) are considered. The linearity of our proposed device improves by 35.5% in view of the compression point in comparison to JLSG MOSFET before the threshold voltage region of operation. The simulation results reveal a substantial enhancement in the linearity performance of the JLSGGC MOSFET. The improved linearity behavior of JLSGGC MOSFET makes it suitable for wireless RF and system-on-chip applications.Analog/RF performance is studied in terms of intrinsic gain (Gm/Gds), cut-off frequency (fT),maximum frequency of oscillation (fmax).Improved analog/RF performances of JLSGGC MOSFET suggests its applications in high frequency operating range.