Study of 5-mask TFT array process with low-cost high-yield high-performance characteristics

Chen, Jr‐Hong; Huang, Ting-Hui; Lu, I‐Min; Chen, Pi‐Fu; Chen, Dou‐I

doi:10.1117/12.389408

Cited by 2 publications

(3 citation statements)

References 5 publications

(5 reference statements)

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“…This is due to the fact that TFT channel structures are different in CL-ES and BCE structures. Generally, BCE-structured TFT channel length are the distance between S/D metal electrodes, and the measured channel length in this study is 5 um [ 21 ]. In CL-ES structure, electrodes are in contact with the a-IGZO nano-film that is stretched at the side of ESL nano-mask.…”

Section: Resultsmentioning

confidence: 99%

“…Moreover, this increased number of thin film layers would increase the inter-layer overlap area and result in the increased parasitic capacitance and decreased opening ratio [ 16 – 18 ]. Although five-mask ES process that produces TFT backplane using half-tone and lift-off technology has been reported recently, this process is not accessible for the production of a-IGZO-based TFT backplane, as their active layer surface is still exposed to process chemicals such as stripper and photoresist in the last step, which may cause considerable contamination to a-IGZO, thus reducing the device quality and the production yield [ 19 – 21 ]. Therefore, the industrial production method for a-IGZO-based TFT backplane with highly uniformity and stability remains challenging.…”

Section: Introductionmentioning

confidence: 99%

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Enhancement of a-IGZO TFT Device Performance Using a Clean Interface Process via Etch-Stopper Nano-layers

et al. 2018

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To overcome the technological and economic obstacles of amorphous indium-gallium-zinc-oxide (a-IGZO)-based display backplane for industrial production, a clean etch-stopper (CL-ES) process is developed to fabricate a-IGZO-based thin film transistor (TFT) with improved uniformity and reproducibility on 8.5th generation glass substrates (2200 mm × 2500 mm). Compared with a-IGZO-based TFT with back-channel-etched (BCE) structure, a newly formed ES nano-layer (~ 100 nm) and a simultaneous etching of a-IGZO nano-layer (30 nm) and source-drain electrode layer are firstly introduced to a-IGZO-based TFT device with CL-ES structure to improve the uniformity and stability of device for large-area display. The saturation electron mobility of 8.05 cm2/V s and the Vth uniformity of 0.72 V are realized on the a-IGZO-based TFT device with CL-ES structure. In the negative bias temperature illumination stress and positive bias thermal stress reliability testing under a ± 30 V bias for 3600 s, the measured Vth shift of CL-ES-structured device significantly decreased to − 0.51 and + 1.94 V, which are much lower than that of BCE-structured device (− 3.88 V, + 5.58 V). The electrical performance of the a-IGZO-based TFT device with CL-ES structure implies that the economic transfer from a silicon-based TFT process to the metal oxide semiconductor-based process for LCD fabrication is highly feasible.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Enhancement of a-IGZO TFT Device Performance Using a Clean Interface Process via Etch-Stopper Nano-layers

et al. 2018

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“…Manufacturing cost control and yield management strategies have become the tendency of great efforts for mass production by most companies and institutions in mainstream LCDs field. One of which is the prefer of 4-Mask process [1,2,3] substitutes for 5-Mask process [4,5] to simplify the manufacturing process architecture by mixed wet and dry etching process (2-Wet and 2-Dry) for the active island and source/data bus-line pattern formation. However, tails beside the second metal layer become the side product of 4-Mask process during current 2-Wet and 2-Dry process, which will reduce the TFT channel size, panel aperture ratio, storage capacity, parasitic capacity and furthermore degenerate TFT properties and panel reliability.…”

Section: Introductionmentioning

confidence: 99%

P‐59: Improving TFT Structure Uniformity in G8.5 LCDs

Liu

Sun

Lin

et al. 2018

Symp Digest of Tech Papers

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Methods for lessening the AS tail and N + tail were systematically investigated in G8.5 glass for LCD product development including novel structure designs and matched 4-Mask process. While matched 4-Mask process had success in tails reducing, I on keeping, stability improving and I off decreasing at higher negative voltage by optimized O 2 ashing process, further efforts were still indispensable. Novel mask structure designs were provided using photoresist thickness modulation method for 4-Mask process architecture to ulteriorly reduce the tails. Less amorphous silicon tail (AS tail) and heavy doped amorphous silicon tail (N + tail) were attained in both inner and outline frame beside the second metal solely by structure design, which limited the scope of N + tail within 0.5 um and AS tail about 1.2um, respectively. What's more, the N + tail could be further decreased by cooperating with the matched 4-Mask process using the optimized recipe.

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Study of 5-mask TFT array process with low-cost high-yield high-performance characteristics

Cited by 2 publications

References 5 publications

Enhancement of a-IGZO TFT Device Performance Using a Clean Interface Process via Etch-Stopper Nano-layers

Enhancement of a-IGZO TFT Device Performance Using a Clean Interface Process via Etch-Stopper Nano-layers

P‐59: Improving TFT Structure Uniformity in G8.5 LCDs

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