Study and Reduction of Variability in 28 nm Fully Depleted Silicon on Insulator Technology

Wei, Zhaopeng; Jacquemod, G.; Lorenzini, P.; Hameau, Frédéric; Foucauld, Emeric de; Leduc, Yves

doi:10.1166/jolpe.2016.1421

Cited by 7 publications

(6 citation statements)

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“…Figure 12 illustrates the layout the QRO with a size of 60*40 µm 2 and Fig. 13 illustrates the complete layout and micrograph of test chip with two QRO and one QCVRO (Quadrature Voltage Controlled Ring Oscillator) not presented in this paper [13].…”

Section: Qro Implementation and Measurementsmentioning

confidence: 99%

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A low power injection-locked CDR using 28 nm FDSOI technology for burst-mode applications

Mao

Charlon

Jacquemod

et al. 2022

Preprint

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In this paper, a low-power Injection-Locked Clock and Data Recovery (ILCDR) using 28 nm FDSOI technology is presented. The back-gate auto-biasing of UTBB-FDSOI transistors allows us to create a QRO (Quadrature Ring Oscillator) reducing both size and power consumption. By injecting a digital signal into this circuit, we realize an Injection-Locked Oscillator (ILO) with low jitter. Thanks to the good performance of this oscillator, we can propose a low power ILCDR with low jitter and fast locking time for burst-mode applications. The main novelty consists in the implementation of a complementary QRO based on back-gate control using FDSOI technology in order to realize a simple and efficient ILCDR circuit. With a Pseudo-Random Binary Sequence (27 PRBS) at 868Mbps, the recovered clock jitter is 18.5 ps (1.6%UIp-p) and the recovered data jitter is 18.7 ps (1.6%UIp-p). With a 0.6 V power supply, the power consumption is 4.67 mA (2.8 mW). The estimated Chip size is around 6600 µm².

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Section: Qro Implementation and Measurementsmentioning

confidence: 99%

“…On the contrary, RO is known to exhibit high phase noise, but this design will address aggressively the size and power consumption reduction. We have proposed a new inverter topology to realize a VCO using FDSOI technology [13].…”

Section: Ro Designmentioning

confidence: 99%

A low power injection-locked CDR using 28 nm FDSOI technology for burst-mode applications

Mao

Charlon

Jacquemod

et al. 2022

Preprint

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“…In this paper, we propose a new topology using some advantages of the FDSOI technology in order to reduce the size of a current mirror. This technology allows realizing new topologies of analog and mixed circuits, offering never reached performances and reducing certain limitations due to the reduction of the channel length [2]. For the current mirror, the aim is to implement very low transistor length, less than 210nm, while maintaining the functionality of a current generator.…”

Section: Basic Implementation Of Current Mirrormentioning

confidence: 99%

“…Thanks to the characteristic of the threshold voltage of UTBB-FDSOI transistors according to the back-gate biasing, we have already taken into account the benefit of the cross-coupled back-gate autobiasing to improve the performances of digital cells [2] and the quality of signal generators [8]. We have yet adapted this concept of BG control to a current mirror.…”

Section: New Design Of Current Mirrormentioning

confidence: 99%

“…On the contrary, ring oscillators (RO, i.e., digital oscillators without passive elements) are known to exhibit high phase noise, but this design will address aggressively the size (only inverters) and power consumption reduction. We have still proposed a new inverter topology to realize a voltage controlled ring oscillator (VCRO) using FDSOI technology [2]. The access to UTBB (Ultra-Thin Body and Box) transistor Back-Gates (BG) offers an extended control of the threshold voltages of the transistors, opening new opportunities to exciting performances.…”

Section: Introductionmentioning

confidence: 99%

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Reducing the Short Channel Effect of Transistors and Reducing the Size of Analog Circuits

Wei

Jacquemod

Leduc

et al. 2019

Active and Passive Electronic Components

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Analog integrated circuits never follow the Moore’s Law. This is particularly right for passive component. Due to the Short Channel Effect, we have to implement longer transistor, especially for analog cell. In this paper, we propose a new topology using some advantages of the FDSOI (Fully Depleted Silicon on Insulator) technology in order to reduce the size of analog cells. First, a current mirror was chosen to illustrate and validate a new design. Measured currents, with 35nm transistor length, have validated our new cross-coupled back-gate topology. Then, a VCRO (Voltage Controlled Ring Oscillator) based on complementary inverter is also used to remove passive components reducing the size of the circuit.

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Application de la technologie FDSOI pour la conception de nouvelles topologies de circuits analogiques et mixtes

Jacquemod¹,

Charlon²,

Wei³

et al. 2019

J3eA

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Pour poursuivre la loi de Moore avec des noeuds technologiques de 22 nm et en deçà, les transistors MOS bulk ont été remplacés par des transistors FinFET ou UTBB-FDSOI. Ces derniers disposent d’une grille arrière permettant de réaliser de nouvelles topologies de circuits analogiques et mixtes, offrant des performances jamais atteintes et réduisant certaines limitations, comme par exemple celles liées à la réduction de la longueur du canal. Partant de la caractéristique de la tension de seuil d’un transistor UTBB-FDSOI en fonction de la polarisation de la grille arrière, nous proposons aux élèves-ingénieurs d’étudier quelques nouvelles topologies de cellules par des simulations statiques et transitoires, associés à des analyses de Monte Carlo pour évaluer l’impact des variations du procédé de fabrication sur leurs performances finales. La première étude concerne la réalisation d’un inverseur en logique complémentaire basé sur le couplage croisé des grilles arrières de deux inverseurs permettant une symétrisation des signaux de sortie complémentaires. Ce concept peut être étendu à toutes les portes logiques et permet de réaliser des oscillateurs en anneau aux performances inédites. Une approche similaire est également appliquée à un miroir de courant permettant de réduire de façon drastique les effets de canal court.

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Study and Reduction of Variability in 28 nm Fully Depleted Silicon on Insulator Technology

Cited by 7 publications

References 0 publications

A low power injection-locked CDR using 28 nm FDSOI technology for burst-mode applications

A low power injection-locked CDR using 28 nm FDSOI technology for burst-mode applications

Reducing the Short Channel Effect of Transistors and Reducing the Size of Analog Circuits

Application de la technologie FDSOI pour la conception de nouvelles topologies de circuits analogiques et mixtes

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