A design method of low-pass (LP) negative group delay (NGD) integrated circuit (IC) implemented in 130-nm BiCMOS technology is investigated. The LP-NGD circuit is composed by RL-network with BiCMOS high Ohmic unsalicided N+poly resistor and symmetrical high current spiral inductor. The design methodology of the investigated LP-NGD circuit is explained by chip layout process. Then, the pre-simulation is performed with the design rule check (DRC) and 225 μm  215 μm layout versus schematic (LVS) approaches. The LP-NGD design feasibility of the BiCMOS IC implementation is validated by AC frequency domain simulation with realistic component implementation constraints. As expected, the ideally calculated and simulated results show NGD of about À100 ps with 1.12 GHz cut-off frequency and À6 dB attenuation. Moreover, the LP-NGD function is also verified with transient analyses with Gaussian pulse and arbitrary waveform signals. As expected, despite the attenuation, the output signal leading and tailing edges appear in time-advance of about À100 ps compared to the input ones. K E Y W O R D S 130-nm BiCMOS technology, design method, low-pass (LP) NGD integrated circuit (IC), negative group delay (NGD), RL-network passive topology