Studies on underfilling components with area array solder terminals in surface mount technology

Abstract

The underfilling of CSP and BGA components with area I array lead free and lead containing solder terminals in surface mount technology has been systematically studied and evaluated. One of the goals of the research was to define the particular requirements that have to be put on CSP/BGA underfill materials and to estimate what level of process reliability for underfilling can be achieved. The knowledge and experience with flip chip underfilling could not be directly transferred to CSP and BGA assemblies due to the differences in material combinations and geometry of the joint gap as well as the differences in the nature and magnitude of the stress. Ageing and stress tests on test assemblies with commercially available and alternative underfill materials highlighted the specific advantages of underfilling CSPs and BGAs. The experimental findings and the simulations results allowed the required property profiles of CSP/BGA underfillers to be defined. From the effects of underfill defects, statements about process reliability could be made

Effect of Properties of Underfill Materials on Thermal Stress Relief in Lead-Free Solder Joint of Chip Size Package

“…In area-array-type electronic packages such as the ball grid array (BGA), chip size package (CSP) and flip chip, the thermal fatigue of a solder joint caused by coefficient of thermal expansion (CTE) mismatch between jointed materials is a very important problem that must be solved to ensure the high reliability of the solder joint [1]. The solder joint of the area-array-type package is often encapsulated with an underfill material to reduce the thermal stress applied in the solder joint under field conditions [2][3][4]. Generally, the thermal stress relief in the solder joint under thermal cycle conditions is investigated by a finite element analysis method (FEM).…”